ADSP-BF531/ADSP-BF532/ADSP-BF533
Clock and Reset Timing
and
describe clock and reset operations. Per
combinations of
CLKIN and clock multipliers/divisors must not result in core/
Table 16. Clock and Reset Timing
Parameter
Timing Requirements
t
CKIN
CLKIN Period
1, 2, 3, 4
t
CKINL
CLKIN Low Pulse
t
CKINH
CLKIN High Pulse
t
WRST
RESET Asserted Pulse Width Low
5
1
2
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Min
25.0
10.0
10.0
11 t
CKIN
Max
100.0
Unit
ns
ns
ns
ns
Applies to PLL bypass mode and PLL nonbypass mode.
CLKIN frequency must not change on the fly.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in
through
Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4
If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN
period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
t
CKIN
CLKIN
t
CKINL
RESET
t
CKINH
t
WRST
Figure 11. Clock and Reset Timing
Rev. E |
Page 25 of 60 |
July 2007
AD [ ANALOG DEVICES ]
