ADSP-BF531/ADSP-BF532
TIMING SPECIFICATIONS
through
describe the timing requirements for
the ADSP-BF531/ADSP-BF532 processor clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock as described in
Table 12. Core Clock Requirements
T
JUNCTION
= 125°C
Min
Max
2.50
3.00
3.39
All
1
Other T
JUNCTION
Min
Max
2.50
2.75
3.00
3.57
4.00
and the voltage controlled oscil-
lator (VCO) operating frequencies described in
describes phase-locked loop operating conditions.
Parameter
t
CCLK
Core Cycle Period (V
DDINT
=1.14 V minimum)
t
CCLK
Core Cycle Period (V
DDINT
=1.045 V minimum)
t
CCLK
Core Cycle Period (V
DDINT
=0.95 V minimum)
t
CCLK
Core Cycle Period (V
DDINT
=0.85 V minimum)
t
CCLK
Core Cycle Period (V
DDINT
=0.8 V )
1
Unit
ns
ns
ns
ns
ns
See
Table 13. Phase-Locked Loop Operating Conditions
Parameter
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
Min
50
Max
Maximum f
CCLK
Unit
MHz
Table 14. Maximum SCLK Conditions
Parameter
1
MBGA/PBGA
f
SCLK
f
SCLK
LQFP
f
SCLK
f
SCLK
1
V
DDEXT
= 1.8 V
CLKOUT/SCLK Frequency (V
DDINT
≥
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
<
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
≥
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
<
1.14 V)
100
100
100
83
V
DDEXT
= 2.5 V
133
100
133
83
V
DDEXT
= 3.3 V
133
100
133
83
Unit
MHz
MHz
MHz
MHz
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.
Rev. D |
Page 23 of 60 |
August 2006
AD [ ANALOG DEVICES ]
