ADSP-BF531/ADSP-BF532
“FI NE” ADJUSTMENT
REQUI RES PLL SEQ UENCING
“CO ARSE” ADJUSTMENT
ON-THE-FLY
BOOTING MODES
The ADSP-BF531/ADSP-BF532 processor has two mechanisms
(listed in
for automatically loading internal L1 instruc-
tion memory after a reset. A third mode is provided to execute
from external memory, bypassing the boot sequence.
Table 8. Booting Modes
÷ 1, 2, 4, 8
CLKIN
PLL
0.5× to 64×
CCLK
VCO
÷ 1 to 15
SCLK
BMODE1–0
00
SCLK
≤
CCLK
SCLK
≤
133 MHz
Figure 8. Frequency Modification Methods
01
10
11
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
1:1
100
100
3:1
400
133
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit FLASH
Boot from SPI host slave mode
Boot from SPI serial EEPROM (8-, 16-, or 24-bit
address range)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous memory bank 0. All configuration set-
tings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM (8-, 16-, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read com-
mands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8-, 16-, or 24-bit addressable EEPROM is detected,
and begins clocking data into the beginning of L1 instruc-
tion memory.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
Signal Name
SSEL3–0
0001
0011
The maximum frequency of the system clock is f
SCLK
. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
SCLK
. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Example Frequency Ratios
Divider Ratio (MHz)
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
Signal Name
CSEL1–0
00
01
10
11
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
Rev. D |
Page 14 of 60 |
August 2006
AD [ ANALOG DEVICES ]
