ADSP-BF531/ADSP-BF532
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF531/
ADSP-BF532 processor allows both the processor’s input volt-
age (V
DDINT
) and clock frequency (f
CCLK
) to be dynamically
controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
power savings factor
V
DDINTRED 2
t
RED
f
CCLKRED
-
-
-
= --------------------
×
⎛
-------------------------
⎞
×
⎛
----------
⎞
f
CCLKNOM
⎝
V
DDINTNOM
⎠ ⎝
t
NOM
⎠
where the variables in the equations are:
f
CCLKNOM
is the nominal core clock frequency
f
CCLKRED
is the reduced core clock frequency
V
DDINTNOM
is the nominal internal supply voltage
V
DDINTRED
is the reduced internal supply voltage
t
NOM
is the duration running at
f
CCLKNOM
t
RED
is the duration running at
f
CCLKRED
The percent power savings is calculated as:
% power savings
=
(
1
–
power savings factor
) ×
100%
Figure 6. Voltage Regulator Circuit
V
D D EX T
100µF
10µH
0.1µF
100µF
1µF
ZHCS1000
2.25V TO 3.6V
INPUT VO LTAGE
RANGE
FDS9431A
V
D D INT
VR
OU T
1–0
EXTERNAL COMPO NENT S
NOTE: VR
OU T
1–0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIG NER SHOULD MINIMIZ E TRACE LENGTH TO FDS9431A.
If an external clock is used, it must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s CLKIN pin.
When an external clock is used, the XTAL pin must be left
unconnected.
Alternatively, because the ADSP-BF531/ADSP-BF532 processor
includes an on-chip oscillator circuit, an external crystal may be
used. The crystal should be connected across the CLKIN and
XTAL pins, with two capacitors connected as shown in
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should
be used.
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85 V to 1.2 V
from an external 2.25 V to 3.6 V supply.
shows the typ-
ical external components required to complete the power
management system.
†
The regulator controls the internal logic
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (V
DDEXT
) supplied. While in hibernation,
V
DDEXT
can still be applied, eliminating the need for external
buffers. The voltage regulator can be activated from this power-
down state either through an RTC wakeup or by asserting
RESET, which will then initiate a boot sequence. The regulator
can also be disabled and bypassed at the user’s discretion.
CLKIN
XTAL
CLKOUT
Figure 7. External Crystal Connections
CLOCK SIGNALS
The ADSP-BF531/ADSP-BF532 processor can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
As shown in
the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 0.5× to 64× multipli-
cation factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
†
See EE-228: Switching Regulator Design Considerations for Blackfin Processors.
Rev. D |
Page 13 of 60 |
August 2006
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