ADSP-BF531/ADSP-BF532
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532 processor pin definitions are listed
in
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 9. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
I/O
I/O
I/O
Timer 0
Timer 1/PPI
Frame Sync1
Timer 2/PPI
Frame Sync2
C
C
C
None
None
None
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
A
A
A
A
B
A
A
None
None
None
None
None
None
None
O
I
O
O
O
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
A
A
A
A
None
Pull-up Required If Function Not Used
None
None
None
O
I/O
O
I
O
O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Bus Request
Bus Grant
Bus Grant Hang
A
A
A
A
None
None
None
Pull-up Required If Function Not Used
None
None
Type Function
Driver
Type
1
Pull-Up/Down Requirement
Byte Enables/Data Masks for Async/Sync Access A
Rev. D |
Page 17 of 60 |
August 2006
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