ADSP-BF531/ADSP-BF532
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The baud rate, serial data format, error code generation and sta-
tus, and interrupts for the UART port are programmable.
The UART programmable features include:
• Supporting bit rates ranging from (f
SCLK
/1,048,576) bits per
second to (f
SCLK
/16) bits per second.
• Supporting data formats from seven bits to 12 bits per
frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f
SCLK
-
UART Clock Rate
= ----------------------------------------------
16
×
UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA) serial infrared physical
layer link specification (SIR) protocol.
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters,
ITU-R 601/656 video encoders and decoders, and other general-
purpose peripherals. The PPI consists of a dedicated input clock
pin, up to three frame synchronization pins, and up to 16 data
pins. The input clock supports parallel data rates up to half the
system clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:
• Active video only – The PPI does not read in any data
between the end of active video (EAV) and start of active
video (SAV) preamble symbols, or any data present during
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.
• Vertical blanking only – The PPI only transfers vertical
blanking interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.
• Entire field – The entire incoming bitstream is read in
through the PPI. This includes active video, control pream-
ble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
PROGRAMMABLE FLAGS (PFx)
The ADSP-BF531/ADSP-BF532 processor has 16 bidirectional,
general-purpose programmable flag (PF15–0) pins. Each pro-
grammable flag can be individually controlled by manipulation
of the flag control, status and interrupt registers:
• Flag direction control register – Specifies the direction of
each individual PFx pin as input or output.
• Flag control and status registers – The ADSP-BF531/
ADSP-BF532 processor employs a “write one to modify”
mechanism that allows any combination of individual flags
to be modified in a single instruction, without affecting the
level of any other flags. Four control registers are provided.
One register is written in order to set flag values, one regis-
ter is written in order to clear flag values, one register is
written in order to toggle flag values, and one register is
written in order to specify a flag value. Reading the flag sta-
tus register allows software to interrogate the sense of the
flags.
• Flag interrupt mask registers – The two flag interrupt mask
registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
Rev. D |
Page 11 of 60 |
August 2006
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