ADSP-2181
P aram eter
Min
Max
Unit
ID MA Wr ite, Long Wr ite Cycle
Timing Requirements:
tIKW
tIKSU
tIKH
IACK Low before Start of Write1
0
ns
ns
ns
IAD15–0 Data Setup before IACK Low2, 3
IAD15–0 Data Hold after IACK Low2, 3
0.5tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW Start of Write to IACK High
1.5tCK
ns
ns
15
NOT ES
1Start of Write = IS Low and IWR Low.
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
3If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH
.
4T his is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 16. IDMA Write, Long Write Cycle
REV. D
–22–
ADI [ ADI ]
