ADSP-2181
CAP ACITIVE LO AD ING
Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2181.
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
25
INPUT
1.5V
1.5V
OR
OUTPUT
20
15
10
Figure 24. Voltage Reference Levels for AC Measure-
m ents (Except Output Enable/Disable)
O utput Enable Tim e
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
5
0
50
0
100
150
– pF
200
250
C
L
Figure 22. Range of Output Rise Tim e vs. Load Capaci-
tance, CL (at Maxim um Am bient Operating Tem perature)
REFERENCE
SIGNAL
tMEASURED
16
tENA
14
12
V
V
OH tDIS
OH
(MEASURED)
(MEASURED)
V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
2.0V
1.0V
OH
OUTPUT
10
8
OL
V
V
OL
OL
tDECAY
(MEASURED)
(MEASURED)
6
4
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
2
0
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 25. Output Enable/Disable
–2
–4
I
0
50
100
150
200
250
OL
C
– pF
L
Figure 23. Range of Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating
Tem perature)
TO
OUTPUT
PIN
+1.5V
50pF
TEST CO ND ITIO NS
O utput D isable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY
as shown in the Output Enable/Disable diagram. T he time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. T he decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
I
OH
Figure 26. Equivalent Device Loading for AC Measure-
m ents (Including All Fixtures)
,
CL × 0.5V
tDECAY
=
iL
from which
tDIS = tMEASURED – tDECAY
REV. D
–26–
ADI [ ADI ]
