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ADSP-21062KS-160 参数 Datasheet PDF下载

ADSP-21062KS-160图片预览
型号: ADSP-21062KS-160
PDF下载: 下载PDF文件 查看货源
内容描述: ADSP- 2106x SHARC DSP单片机系列 [ADSP-2106x SHARC DSP Microcomputer Family]
分类和应用:
文件页数/大小: 48 页 / 368 K
品牌: ADI [ ADI ]
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ADSP-21062/ADSP-21062L  
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —  
Pin 3 must be removed from the header. The pins must be  
0.025 inch square and at least 0.20 inch in length. Pin spacing  
should be 0.1 × 0.1 inches. Pin strip headers are available from  
vendors such as 3M, McKenzie, and Samtec.  
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE  
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1  
JTAG test access port of the ADSP-2106x to monitor and  
control the target board processor during emulation. The EZ-  
ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,  
TRST, TDI, TDO, EMU, and GND signals be made acces-  
sible on the target system via a 14-pin connector (a 2 row × 7  
pin strip header) such as that shown in Figure 5. The EZ-ICE  
probe plugs directly onto this connector for chip-on-board  
emulation. You must add this connector to your target board  
design if you intend to use the ADSP-2106x EZ-ICE. The total  
trace length between the EZ-ICE connector and the furthest  
device sharing the EZ-ICE JTAG pin should be limited to 15  
inches maximum for guaranteed operation. This length restric-  
tion must include EZ-ICE JTAG signals that are routed to one  
or more ADSP-2106x devices, or a combination of ADSP-  
2106x devices and other JTAG devices on the chain.  
The BTMS, BTCK, BTRST, and BTDI signals are provided so  
that the test access port can also be used for board-level testing.  
When the connector is not being used for emulation, place  
jumpers between the BXXX pins and the XXX pins as shown in  
Figure 5. If you are not going to use the test access port for  
board testing, tie BTRST to GND and tie or pull up BTCK to  
VDD. The TRST pin must be asserted after power-up (through  
BTRST on the connector) or held low for proper operation of  
the ADSP-2106x. None of the BXXX pins (Pins 5, 7, 9, 11) are  
connected on the EZ-ICE probe.  
The JTAG signals are terminated on the EZ-ICE probe as follows:  
Signal Termination  
1
3
5
2
4
6
TMS  
TCK  
Driven through 22 Resistor (16 mA Driver)  
Driven at 10 MHz through 22 Resistor (16 mA  
Driver)  
EMU  
GND  
KEY (NO PIN)  
CLKIN (OPTIONAL)  
TMS  
TRST* Active Low Driven through 22 Resistor (16 mA  
Driver) (Pulled Up by On-Chip 20 kResistor)  
BTMS  
TDI  
TDO  
Driven by 22 Resistor (16 mA Driver)  
7
9
8
One TTL Load, Split Termination (160/220)  
TCK  
BTCK  
CLKIN One TTL Load, Split Termination (160/220)  
EMU  
10  
12  
Active Low 4.7 kPull-Up Resistor, One TTL Load  
(Open-Drain Output from the DSP)  
BTRST  
TRST  
11  
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at  
software start-up. After software start-up, TRST is driven high.  
BTDI  
GND  
TDI  
13  
14  
TDO  
TOP VIEW  
Figure 5. Target Board Connector For ADSP-2106x  
EZ-ICE Emulator (Jumpers in Place)  
JTAG  
ADSP-2106x  
ADSP-2106x  
#1  
DEVICE  
n
(OPTIONAL)  
TDI  
TDO  
TDO  
TDO  
TDI  
TDI  
TDI  
EZ-ICE  
JTAG  
CONNECTOR  
OTHER  
JTAG  
CONTROLLER  
TCK  
TMS  
EMU  
TRST  
TDO  
CLKIN  
OPTIONAL  
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems  
REV. C  
–11–  
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