ADSP-21062/ADSP-21062L
Pin
Type
I/O
Function
TFSx
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
RFSx
I/O
LxDAT3-0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxCLK
LxACK
EBOOT
I/O
I/O
I
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. When EBOOT is high, the ADSP-21062 is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. When LBOOT is high, the ADSP-21062 is configured for link port booting. When
LBOOT is low, the ADSP-21062 is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
BMS
I/O/T*
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-
cates that no booting will occur and that ADSP-21062 will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
CLKIN
I
Clock In. External clock input to the ADSP-21062. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-21062 to a known state and begins program execution at the
program memory location specified by the hardware reset vector address. This input must be asserted
(low) at power-up.
TCK
TMS
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21062. TRST has a 20 kΩ internal pull-up resistor.
EMU
ICSA
VDD
GND
NC
O
O
P
Emulation Status. Must be connected to the ADSP-21062 EZ-ICE target board connector only.
Reserved, leave unconnected.
Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins)
Power Supply Return. (30 pins)
G
Do Not Connect. Reserved pins which must be left open and unconnected.
REV. C
–10–
ADI [ ADI ]
