ADSP-21061/ADSP-21061L
S®
GENERAL NOTE
Figure 1 shows a block diagram of the ADSP-21061/ADSP-
21061L, illustrating the following architectural features:
This data sheet represents production released specifications
for the ADSP-21061 5 V and ADSP-21061L 3.3 V proces-
sors. ADSP-21061 is used throughout this data sheet to refer to
both devices unless expressly noted.
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
GENERAL DESCRIPTION
The ADSP-21061 is a member of the powerful SHARC family
of floating point processors. The SHARC—Super Harvard
Architecture Computer—are signal processing microcomputers
that offer new capabilities and levels of integration and perfor-
mance. The ADSP-21061 is a 32-bit processor optimized for
high performance DSP applications. The ADSP-21061 com-
bines the ADSP-21000 DSP core with a dual-ported on-chip
SRAM and an I/O processor with a dedicated I/O bus to form a
complete system-in-a-chip.
1 Mbit On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port & Multiprocessor Interface
DMA Controller
Serial Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time operating at up
to 50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table I shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
Table I. ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
0.37 ms
18,221 Cycles
The ADSP-21061 SHARC combines a high-performance float-
ing-point DSP core with integrated, on-chip system features,
including a 1 Mbit SRAM memory, host processor interface,
DMA controller, serial ports and parallel bus connectivity for
glueless DSP multiprocessing.
20 ns
80 ns
120 ns
180 ns
1 Cycle
4 Cycles
6 Cycles
9 Cycles
Inverse Square Root (1/√x)
DMA Transfer Rate
300 Mbytes/s
REV. B
–3–
ADI [ ADI ]
