ADSP-21061/ADSP-21061L
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 is code and
function compatible with the ADSP-21060/ADSP-21062 and
the ADSP-21020.
Instruction Cache
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier op-
erations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point and 32-bit fixed-point data formats.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The ADSP-21061 two
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers (16 primary register sets, 16 secondary). The
DAGs automatically handle address pointer wraparound, reduc-
ing overhead, increasing performance and simplifying imple-
mentation. Circular buffers can start and end at any memory
location.
ADSP-21061/
ADSP-21061L
CS
1x CLOCK
TO GND
CLKIN
EBOOT
LBOOT
BMS
BOOT
EPROM
(OPTIONAL)
ADDR
DATA
3
IRQ
2-0
Flexible Instruction Set
4
ADDR
FLAG
31-0
ADDR
DATA
OE
WE
ACK
CS
3-0
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21061 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
TIMEXP
MEMORY
AND
PERIPHERALS
DATA
47-0
RD
WR
TCLK0
RCLK0
TFS0
RSF0
DT0
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
ACK
MS
3-0
ADSP-21061 FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21061
adds the following architectural features:
PAGE
SBTS
SW
DR0
DMA DEVICE
(OPTIONAL)
DATA
ADRCLK
TCLK1
RCLK1
TFS1
RSF1
DT1
DMAR
Dual-Ported On-Chip Memory
1-2
SERIAL
DEVICE
(OPTIONAL)
DMAG
1-2
The ADSP-21061 contains 1 megabit of on-chip SRAM, orga-
nized as two banks of 0.5 Mbits each. Each bank has eight 16-
bit columns with 4K 16-bit words per column. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 Memory Map).
CS
HBR
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
DR1
HBG
REDY
RPBA
BR
ADDR
DATA
1-6
ID
2-0
CPA
RESET JTAG
7
On the ADSP-21061, the memory can be configured as a maxi-
mum of 32K words of 32-bit data, 64K words for 16-bit data,
16K words of 48-bit instructions (and 40-bit data) or combina-
tions of different word sizes up to 1 megabit. All the memory
can be accessed as 16-bit, 32-bit or 48-bit.
Figure 2. ADSP-21061/ADSP-21061L System
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
A 16-bit floating-point storage format is supported that effec-
tively doubles the amount of data that may be stored on chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores in-
structions and data, using the PM bus for transfers. Using the
DM and PM buses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21061’s external port.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
REV. B
–4–
ADI [ ADI ]
