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ADSP-21061LKB-160 参数 Datasheet PDF下载

ADSP-21061LKB-160图片预览
型号: ADSP-21061LKB-160
PDF下载: 下载PDF文件 查看货源
内容描述: ADSP- 2106x SHARC DSP单片机系列 [ADSP-2106x SHARC DSP Microcomputer Family]
分类和应用: 外围集成电路时钟
文件页数/大小: 47 页 / 366 K
品牌: ADI [ ADI ]
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ADSP-21061/ADSP-21061L  
PIN DESCRIPTIONS  
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left  
floating. These pins have a logic-level hold circuit that prevents  
the input from floating internally.  
ADSP-21061 pin definitions are listed below. Inputs identified  
as synchronous (S) must meet timing requirements with respect  
to CLKIN (or with respect to TCK for TMS, TDI). Inputs  
identified as asynchronous (A) can be asserted asynchronously  
to CLKIN (or to TCK for TRST).  
I = Input  
(O/D) = Open Drain O = Output  
G = Ground (A/D) = Active Drive  
S = Synchronous  
P = Power Supply  
A = Asynchronous  
Unused inputs should be tied or pulled to IVDD or IGND,  
except for ADDR31-0, DATA47-0, FLAG3-0, SW and inputs that  
have internal pull-up or pull-down resistors (CPA, ACK, DTx,  
T = Three-State (when SBTS is asserted, or when the  
ADSP-2106x is a bus slave)  
PIN FUNCTION DESCRIPTIONS  
Pin  
Type  
Function  
ADDR31-0  
I/O/T  
External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals  
on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the  
internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a  
host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.  
DATA47-0  
I/O/T  
O/T  
External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins.  
The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point  
data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of  
the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on un-  
used DATA pins are not necessary.  
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks  
of external memory. Memory bank size must be defined in the ADSP-21061’s system control regis-  
ter (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as  
the other address lines. When no external memory access is occurring the MS3-0 lines are inactive;  
they are active, however, when a conditional memory access instruction is executed, whether or not the  
condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory  
(Bank 0). In a multiprocessor system the MS3-0 lines are output by the bus master.  
MS3-0  
RD  
I/O/T  
I/O/T  
O/T  
Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external  
memory devices or from the internal memory of other ADSP-21061s. External devices (including  
other ADSP-21061s) must assert RD to read from the ADSP-21061’s internal memory. In a multi-  
processor system RD is output by the bus master and is input by all other ADSP-21061s.  
Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory  
devices or to the internal memory of other ADSP-21061s. External devices must assert WR to write to  
the ADSP-21061’s internal memory. In a multiprocessor system WR is output by the bus master and is  
input by all other ADSP-21061s.  
DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page  
boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory con-  
trol register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE  
signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the  
bus master.  
WR  
PAGE  
ADRCLK  
O/T  
Address Clock for synchronous external memories. Addresses on ADDR31-0 are valid before the  
rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.  
SW  
I/O/T  
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory  
devices (including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indica-  
tion of an impending write cycle, which can be aborted if WR is not later asserted (e.g. in a conditional  
write instruction). In a multiprocessor system, SW is output by the bus master and is input by all other  
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the  
same time as the address output. A host processor using synchronous writes must assert this pin when  
writing to the ADSP-21061(s).  
ACK  
I/O/S  
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external  
memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off  
completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add  
wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave  
ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal  
memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it  
was last driven to.  
REV. B  
–9–