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ADSP-21061LKB-160 参数 Datasheet PDF下载

ADSP-21061LKB-160图片预览
型号: ADSP-21061LKB-160
PDF下载: 下载PDF文件 查看货源
内容描述: ADSP- 2106x SHARC DSP单片机系列 [ADSP-2106x SHARC DSP Microcomputer Family]
分类和应用: 外围集成电路时钟
文件页数/大小: 47 页 / 366 K
品牌: ADI [ ADI ]
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ADSP-21061/ADSP-21061L  
DMA Controller  
6 DMA Channels  
Multiprocessing  
Glueless Connection for Scalable DSP Multiprocessing  
Architecture  
Distributed On-Chip Bus Arbitration for Parallel Bus  
Connect of Up To Six ADSP-21061s Plus Host  
300 Mbytes/s Transfer Rate Over Parallel Bus  
Background DMA Transfers at 50 MHz, in Parallel with  
Full-Speed Processor Execution  
Performs Transfers Between ADSP-21061 Internal Memory  
and External Memory, External Peripherals, Host  
Processor, or Serial Ports  
Serial Ports  
Host Processor Interface  
Efficient Interface to 16- and 32-Bit Microprocessors  
Host can Directly Read/Write ADSP-21061 Internal Memory  
Two 40 Mbit/s Synchronous Serial Ports  
Independent Transmit and Receive Functions  
3- to 32-Bit Data Word Width  
-Law/A-Law Hardware Companding  
TDM Multichannel Mode  
Multichannel Signaling Protocol  
TABLE OF CONTENTS  
ADSP-21061L EZ-ICE Emulator (Jumpers in Place) . . . 12  
Figure 6. JTAG Scan Path Connections for Multiple  
ADSP-21061/ADSP-21061L Systems . . . . . . . . . . . . . . . 12  
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3  
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4  
ADSP-21061 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . . 8  
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
TARGET BOARD CONNECTOR FOR EZ-ICE®  
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
RECOMMENDED OPERATING CONDITIONS (5V) . 14  
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 14  
POWER DISSIPATION ADSP-21061 (5 V) . . . . . . . . . . . . 15  
RECOMMENDED OPERATING CONDITIONS (3.3V) 16  
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 16  
POWER DISSIPATION ADSP-21061L (3.3 V) . . . . . . . . . 17  
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 18  
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18  
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 21  
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 22  
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 23  
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 25  
Multiprocessor Bus Request and Host Bus Request . . . . . 26  
Asynchronous Read/Write—Host to ADSP-21061 . . . . . . 28  
Three-State Timing—Bus Master, Bus Slave,  
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 37  
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 38  
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 41  
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 42  
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 43, 44  
ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA)  
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout . . . . . 46  
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 47  
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Figure 7. JTAG Clocktree for Multiple ADSP-21061/  
ADSP-21061L Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 21  
Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 22  
Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 24  
Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25  
Figure 17. Multiprocessor Bus Request and Host Bus  
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28  
Figure 18b. Asynchronous Read/Write—Host to  
ADSP-21061/ADSP-21061L . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 19a. Three-State Timing (Bus Transition Cycle,  
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 19b. Three-State Timing (Host Transition Cycle) . . 31  
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 33  
Figure 21. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 22. External Late Frame Sync . . . . . . . . . . . . . . . . . 36  
Figure 23. JTAG Test Access Port and Emulation . . . . . . . 37  
Figure 24. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 39  
Figure 25. Equivalent Device Loading for AC Measurements  
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 26. Voltage Reference Levels for AC Measurements  
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . . 39  
Figure 27. ADSP-2106x Typical Drive Currents  
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 28. Typical Output Rise Time (10%–90% VDD) vs.  
Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . 40  
Figure 29. Typical Output Rise Time (0.8 V–2.0 V) vs. Load  
Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 30. Typical Output Delay or Hold vs. Load Capacitance  
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . 40  
Figure 31. ADSP-2106x Typical Drive Currents  
FIGURES  
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 32. Typical Output Rise Time (10%–90% VDD) vs.  
Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . 40  
Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs. Load  
Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 34. Typical Output Delay or Hold vs. Load Capacitance  
(at Maximum Case Temperature) (VDD = 3.3 V) . . . . . . . 41  
Figure 1. ADSP-21061/ADSP-21061L Block Diagram . . . . 1  
Figure 2. ADSP-21061/ADSP-21061L System . . . . . . . . . . . 4  
Figure 3. Multiprocessing System . . . . . . . . . . . . . . . . . . . . . 6  
Figure 4. ADSP-21061/ADSP-21061L Memory Map . . . . . 7  
Figure 5. Target Board Connector For ADSP-21061/  
EZ-ICE is a registered trademark of Analog Devices, Inc.  
REV. B  
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