ADM8690–ADM8695
RESET O utput
RAM Wr ite P r otection
T he internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when VCC is below 4.65 V (4.4 V for ADM8693). An internal
timer holds RESET low for 50 ms (200 ms for the ADM8695)
after VCC rises above 4.65 V (4.4 V for ADM8693). T his pre-
vents repeated toggling of RESET even if the 5 V power drops
out and recovers with each power line cycle.
T he ADM8691/ADM8693/ADM8695 CEOUT line drives the
Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for ADM8693) reset
threshold.
If VCC falls below the reset threshold, CEOUT goes high, inde-
pendent of the logic level at CEIN. T his prevents the micropro-
cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
T he crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. T he power-up RESET pulse lasts 50 ms (200 ms for the
ADM8695) to allow for this oscillator start-up time. If a differ-
ent reset pulse width is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4. T he manual reset switch and the
0.1 µF capacitor connected to the reset line can be omitted if a
manual reset is not needed. An inverted, active high, RESET
output is also available.
Watchdog Tim er
T he microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 seconds
to verify proper software execution. If a hardware or software
failure occurs such that WDI is not toggled, the ADM8691/
ADM8693 will issue a 50 ms (200 ms for ADM8695) RESET
pulse after 1.6 seconds. T his typically restarts the micro-
processor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4.
P ower Fail D etector
T he +5 V VCC power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R1 and R2, the micro-
processor will have the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be gen-
erated if the unregulated dc input to the 5 V regulator is avail-
able for monitoring. T his will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.
T he Watchdog Output (WDO) goes low if the watchdog timer
is not serviced within its timeout period. Once WDO goes low,
it remains low until a transition occurs at WDI. T he watchdog
timer feature can be disabled by leaving WDI unconnected.
T he RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
–12–
REV. 0
ADI [ ADI ]
