Data Sheet
SPECIFICATIONS
ADF4106
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RF
IN
)
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
REF
IN
Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
INH
, I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OH
, Output High Voltage
I
OH
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
P
I
DD7
(AI
DD
+ DI
DD
)
I
DD8
(AI
DD
+ DI
DD
)
I
DD9
(AI
DD
+ DI
DD
)
I
P
Power-Down Mode
(AI
DD
+ DI
DD
)
B Version
0.5/6.0
–10/0
300
325
20/300
0.8/V
DD
10
±100
104
B Chips
(typ)
0.5/6.0
–10/0
300
325
20/300
0.8/V
DD
10
±100
104
Unit
GHz min/max
dBm min/max
MHz max
MHz max
MHz min/max
V p-p min/max
pF max
μA max
MHz max
Test Conditions/Comments
See Figure 18 for input circuit
For lower frequencies, ensure
slew rate (SR) > 320 V/μs
P=8
P = 16
For f < 20 MHz, ensure SR > 50 V/μs
Biased at AV
DD
/2 (see Note 5
ABP = 0, 0 (2.9 ns antibacklash pulse width)
Programmable, see Table 9
With R
SET
= 5.1 kΩ
With R
SET
= 5.1 kΩ
See Table 9
1 nA typical; T
A
= 25°C
0.5 V ≤ V
CP
≤ V
P
− 0.5 V
0.5 V ≤ V
CP
≤ V
P
− 0.5 V
V
CP
= V
P
/2
5
625
2.5
3.0/11
2
2
1.5
2
1.4
0.6
±1
10
1.4
V
DD
− 0.4
100
0.4
2.7/3.3
AV
DD
AV
DD
/5.5
11
11.5
13
0.4
10
5
625
2.5
3.0/11
2
2
1.5
2
1.4
0.6
±1
10
1.4
V
DD
− 0.4
100
0.4
2.7/3.3
AV
DD
AV
DD
/5.5
9.0
9.5
10.5
0.4
10
mA typ
μA typ
% typ
kΩ typ
nA max
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
μA max
V max
V min/V max
V min/V max
mA max
mA max
mA max
mA max
μA typ
Open-drain output chosen, 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
I
OL
= 500 μA
AV
DD
≤ V
P
≤ 5.5V
9.0 mA typ
9.5 mA typ
10.5 mA typ
T
A
= 25°C
Rev. E | Page 3 of 24
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