Data Sheet
FEATURES
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
P
) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
PLL Frequency Synthesizer
GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REF
IN
frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
AV
DD
DV
DD
FUNCTIONAL BLOCK DIAGRAM
V
P
CPGND
REFERENCE
14-BIT
R COUNTER
14
R COUNTER
LATCH
CLK
DATA
LE
24-BIT INPUT
REGISTER
FUNCTION
LATCH
A, B COUNTER
LATCH
13
13-BIT
B COUNTER
LOAD
PRESCALER
P/P + 1
LOAD
6-BIT
A COUNTER
M3 M2 M1
SD
OUT
LOCK
DETECT
CURRENT
SETTING 1
CPI3 CPI2 CPI1
CURRENT
SETTING 2
CPI6 CPI5 CPI4
HIGH Z
19
AV
DD
MUX
MUXOUT
PHASE
FREQUENCY
DETECTOR
R
SET
REF
IN
CHARGE
PUMP
CP
22
FROM
SD
OUT
FUNCTION
LATCH
N = BP + A
RF
IN
A
RF
IN
B
ADF4106
02720-001
6
CE
AGND
DGND
Figure 1.
Rev. E
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