Data Sheet
ADF4106
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
V
R
P
SET
CP
DV
DD
PIN 1
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
MUXOUT
LE
CPGND
AGND
INDICATOR
ADF4106
ADF4106
TOP VIEW
TOP VIEW 13
(Not to Scale)
12
RF B 4
IN
RF A 5
IN
DATA
CLK
RF
B
IN
IN
11
10
9
RF
A
CE
AV
DD
DGND
REF
IN
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
Figure 3. 16-Lead TSSOP Pin Configuration
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Pin No.
TSSOP
LFCSP
Mnemonic Function
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
RSET
ICP MAX
=
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn
drives the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
10
9, 10
11
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
11
12
13
14
15
16
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
13
DATA
LE
14
15
MUXOUT
DVDD
VP
16, 17
18
EP
Exposed Pad. The exposed pad must be connected to AGND.
Rev. E | Page 7 of 24
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