ADF4001
INTERFACING
ADSP-2181 Interface
The ADF4001 family has a simple SPI® compatible serial inter-
face for writing to the device. SCLK, SDATA, and LE control
the data transfer. When LE (latch enable) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of SCLK will be transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
Figure 12 shows the interface between the ADF4001 family and
the ADSP-21xx digital signal processor. The ADF4001 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
autobuffered mode, and then write to the transmit register of
the DSP. This last operation initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 ms. This is certainly more than adequate
for systems with typical lock times in hundreds of microseconds.
ADuC812 Interface
ADSP-21xx
SCLK
ADF4001
Figure 11 shows the interface between the ADF4001 family and
the ADuC812 MicroConverter®. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4001 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
SCLK
SDATA
DT
LE
CE
TFS
I/O FLAGS
MUXOUT
(LOCK DETECT)
On first applying power to the ADF4001 family, it needs three
writes (one each to the R counter latch, the N counter latch, and
the initialization latch) for the output to become active.
Figure 12. ADSP-21xx to ADF4001 Family Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip package (CP-20) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maxi-
mum rate at which the output frequency can be changed will
be 166 kHz.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edge of the pad pattern. This will ensure that
shorting is avoided.
ADuC812
ADF4001
SCLK
SCLOCK
MOSI
SDATA
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
LE
CE
I/O PORTS
MUXOUT
(LOCK DETECT)
The user should connect the printed circuit board thermal pad
to AGND.
Figure 11. ADuC812 to ADF4001 Family Interface
B
REV.
–15–
ADI [ ADI ]
