ADF4001
COHERENT CLOCK GENERATION
13MHz SYSTEM
ꢁR1
ꢁ4
CLOCK FOR GSM
REF
IN
When testing A/D converters, it is often advantageous to use a
coherent test system, that is, a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
function. Figure 8 shows how the ADF4001 can be used to handle
all the possible combinations of the input signal frequency and
sampling rate. The first ADF4001 is phase locked to a VCO. The
output of the VCO is also fed into the N divider of the second
ADF4001. This results in both ADF4001s being coherent with
the REFIN. Since the REFIN comes from the signal generator, the
MUXOUT signal of the second ADF4001 is coherent with the fIN
frequency to the ADC. This is used as fS, the sampling clock.
CP
RF
RF
LOOP
FILTER
VCXO
13MHz
IN
ꢁ1
ꢁN1
ADF4001
19.44MHz SYSTEM
CLOCK FORWCDMA
ꢁR2
REF
IN
ꢁ1300
CP
RF
RF
VCXO
19.44MHz
LOOP
FILTER
52MHz
MASTER
CLOCK
IN
ꢁ486
ꢁN2
ADF4001
f
IN
19.2MHz SYSTEM
CLOCK FOR CDMA
ꢁR3
ꢁ65
A/D
CONVERTER
UNDER
f
= (f ꢀ N1)/(R1 ꢀ N2)
A
REF
S
IN
IN
IN
SINE
CP
RF
RF
LOOP
FILTER
VCXO
19.2MHz
OUTPUT
TEST
BRUEL &
KJAER
MODEL 1051
SAMPLING
CLOCK
IN
ꢁ24
ꢁN3
f
S
REF
IN
ADF4001
SQUARE
OUTPUT
ꢁR1
CP
RF
RF
VCO
100MHz
LOOP
FILTER
Figure 9. Tri-Band System Clock Generation
IN
ꢁN1
ꢁN2
V
P
ADF4001
RF
IN
POWER-DOWN CONTROL
NC7S04
MUXOUT
V
S
DD
ADF4001
RF
OUT
V
DD
IN
ADG702
Figure 8. Coherent Clock Generator
D
GND
100pF
TRI-BAND CLOCK GENERATION CIRCUIT
15
16
In multiband applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz master clock. The low RF
fMIN specification and the ability to program R and N values as
low as ꢀ 1 makes the ADF4001 suitable for this. Other fOUT
clock frequencies can be realized using the formula
7
10
CE
CP
18ꢂ
18ꢂ
V
CC
AV
DV
V
P
DD
DD
100pF
18ꢂ
2
1
LOOP
FILTER
VCO
OR
VCXO
FREF
IN
R
SET
GND
10kꢂ
ADF4001
100pF
6
5
RF
A
B
IN
fOUT = REFIN × N ÷ R
(
)
51ꢂ
RF
IN
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic 1 is applied to the IN input.
The low cost switch is available in both SOT-23 and micro
SOIC packages.
100pF
CPGND AGND DGND
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROMTHE
DIAGRAM INTHE INTEREST OF GREATER CLARITY.
3
4
9
Figure 10. Local Oscillator Shutdown Circuit
–14–
B
REV.
ADI [ ADI ]
