ADF4001
Table IV. N Counter Latch Map
CP GAIN
RESERVED
13-BIT N COUNTER
RESERVED
CONTROL
BITS
DB23 DB22
X
X
DB21
G1
DB20
N13
DB19
N12
DB18
N11
DB17
N10
DB16
N9
DB15
N8
DB14
N7
DB13
N6
DB12
N5
DB11
N4
DB10
N3
DB9
N2
DB8
N1
DB7
X
DB6
X
DB5
X
DB4
X
DB3
X
DB2
X
DB1
C2 (0)
DB0
C1 (1)
X = DON’T CARE
N13
0
0
0
0
.
.
.
1
1
1
1
N12
0
0
0
0
.
.
.
1
1
1
1
N11
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
N3
0
0
0
1
.
.
.
1
1
1
1
N2
0
1
1
0
.
.
.
0
0
1
1
N1
1
0
1
0
.
.
.
0
1
0
1
N COUNTER DIVIDE RATIO
1
2
3
4
.
.
.
8188
8189
8190
8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
0
0
1
1
0
1
0
1
OPERATION
CHARGE PUMP CURRENT SETTING
1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON’T CARE BITS.
REV.
B
–9–
AD [ ANALOG DEVICES ]
