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AD9959BCPZ-REEL7 参数 Datasheet PDF下载

AD9959BCPZ-REEL7图片预览
型号: AD9959BCPZ-REEL7
PDF下载: 下载PDF文件 查看货源
内容描述: [4 Channel 500 MSPS DDS with 10-bit DACs]
分类和应用: 时钟数据分配系统外围集成电路
文件页数/大小: 46 页 / 692 K
品牌: AD [ ANALOG DEVICES ]
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AD9959
Parameter
Residual Phase Noise @ 100.3 MHz (f
OUT
)
with
REFCLK Multiplier Enabled 5×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 15.1 MHz (f
OUT
)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 40.1 MHz (f
OUT
)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 75.1 MHz (f
OUT
)
with REFCLK
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 100.3 MHz (f
OUT
)
with
REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Serial Clock (SCLK)
Minimum SCLK Pulse Width Low (t
PWL
)
Minimum SCLK Pulse Width High (t
PWH
)
Minimum Data Setup Time (t
DS
)
Minimum Data Hold Time
Minimum CS Setup Time (t
PRE
)
Minimum Data Valid Time for Read Operation
MISCELLANEOUS TIMING CHARACTERISTICS
MASTER_RESET Minimum Pulse Width
I/O_UPDATE Minimum Pulse Width
Minimum Setup Time (I/O_UPDATE to SYNC_CLK)
Minimum Hold Time (I/O_UPDATE to SYNC_CLK)
Minimum Setup Time (Profile Inputs to SYNC_CLK)
Minimum Hold Time (Profile Inputs to SYNC_CLK)
Minimum Setup Time (SDIO Inputs to SYNC_CLK)
Minimum Hold Time (SDIO Inputs to SYNC_CLK)
Propagation Time Between REF_CLK and SYNC_CLK
Profile Pin Toggle Rate
CMOS LOGIC INPUTS
V
IH
V
IL
Logic 1 Current
Logic 0 Current
Input Capacitance
Min
Typ
Max
Unit
Test Conditions/Comments
−120
−130
−135
−129
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−127
−136
−139
−138
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−117
−128
−132
−130
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−121
−125
−123
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−107
−119
−121
−119
200
1.6
2.2
2.2
0
1.0
12
1
1
4.8
0
5.4
0
2.5
0
2.25
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
ns
ns
ns
ns
ns
ns
Min pulse width = 1 sync clock period
Min pulse width = 1 sync clock period
Rising edge to rising edge
Rising edge to rising edge
3.5
5.5
2
ns
ns
ns
ns
ns
ns
ns
Sync
clocks
V
V
μA
μA
pF
2.0
3
−12
2
0.8
12
Rev. B | Page 6 of 44