AD9959
Pin No.
Mnemonic
I/O1
Description
24
CLK_MODE_SEL
I
Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V.
When high (1.8 V), the oscillator section is enabled to accept a crystal as the
REF_CLK source. When low, the oscillator section is bypassed.
27
LOOP_FILTER
I
Connects to the external zero compensation network of the PLL loop filter.
Typically, the network consists of a 0 Ω resistor in series with a 680 pF capacitor
tied to AVDD.
29
CH0_IOUT
CH0_IOUT
CH1_IOUT
CH1_IOUT
P0 to P3
O
O
O
O
I
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Data pins used for modulation (FSK, PSK, ASK), to start/stop the sweep accumulators
or used to ramp up/ramp down the output amplitude. The data is synchronous to
the SYNC_CLK (Pin 54). The data inputs must meet the setup and hold time
requirements of the SYNC_CLK. The functionality of these pins is controlled by the
profile pin configuration (PPC) bits (FR1[14:12]).
30
35
36
40 to 43
46
I/O_UPDATE
I
A rising edge transfers data from the serial I/O port buffer to active registers.
I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the
setup and hold time requirements of the SYNC_CLK to guarantee a fixed pipeline
delay of data to the DAC output; otherwise, a 1 SYNC_CLK period of pipeline
uncertainty exists. The minimum pulse width is one SYNC_CLK period.
47
48
CS
I
I
Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI).
SCLK
Serial Data Clock for I/O Operations. Data bits are written on the rising edge of
SCLK and read on the falling edge of SCLK.
49
50
51, 52
DVDD_I/O
SDIO_0
SDIO_1, SDIO_2
I
3.3 V Digital Power Supply for SPI Port and Digital I/O.
Data Pin SDIO_0 is dedicated to the serial port I/O only.
Data Pin SDIO_1 and Data Pin SDIO_2 can be used for the serial I/O port or used to
initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude.
I/O
I/O
53
54
SDIO_3
I/O
Data Pin SDIO_3 can be used for the serial I/O port or to initiate a ramp-up/ramp-down
(RU/RD) of the DAC output amplitude. In single-bit or 2-bit modes, SDIO_3 is used
for SYNC_I/O. If the SYNC_I/O function is not used, tie to ground or Logic 0. Do not
let SDIO_3 float in single-bit or 2-bit modes.
The SYNC_CLK runs at one-fourth the system clock rate; it can be disabled. I/O_UPDATE
or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline
delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must meet the
setup and hold time requirements to the rising edge of SYNC_CLK; otherwise, a 1
SYNC_CLK period of uncertainty occurs.
SYNC_CLK
O
1 I = input, O = output.
Rev. B | Page 10 of 44
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