AD9888
Table V. Control Register Map (continued)
Register Name Function
Read and
Write or
Address Read Only Bits Value
Hex
Default
14H
RO
7:0
Sync Detect
Bit 7—Hsync Detect. It is set to Logic 1 if Hsync is present on the analog
interface, else it is set to Logic 0.
Bit 6—AHS: Active Hsync. This bit indicates which analog Hsync is being
used. (Logic 0 = Hsync input pin, Logic 1 = Hsync from sync-on-green.)
Bit 5—Input Hsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 4—Vsync detect. It is set to Logic 1 if Vsync is present on the analog
interface, else it is set to Logic 0.
Bit 3—AVS: Active Vsync. This bit indicates which analog Vsync is being
used. (Logic 0 = Vsync input pin, Logic 1 = Vsync from sync separator.)
Bit 2—Output Vsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 1—Sync-on-Green Detect. It is set to Logic 1 if sync is present on the
green video input, else it is set to 0.
Bit 0—Input COAST Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
15H
R/W
7:0
1*******
*1******
**0*****
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. (Logic 0 = single-channel mode, Logic 1 = dual-channel mode.)
Bit 6—Output Mode. Determine interleaved or parallel output mode.
(Logic 0 = interleaved mode, Logic 1 = parallel mode.)
Bit 5—A/B Invert. Determines which port outputs the first data byte after
Hsync. (Logic 0 = A port, Logic 1 = B port.)
***0****
****0***
*****11*
*******0
Bit 4—4:2:2 Output Formatting Mode.
Bit 3—Input Mux Control.
Bits [2:1]—Input Bandwidth.
Bit 0—External Clock. Shuts down PLL and allows external clock to drive the
part. (Logic 0 = use internal PLL, Logic 1 = bypassing of the internal PLL.)
16H
17H
18H
19H
NOTE
R/W
R/W
RO
7:0
7:3
7:0
7:0
11111111 Test Register
00000000 Test Register
Test Register
Must be set to 11111110 for proper operation.
Must be set to default for proper operation.
RO
Test Register
1. The AD9888 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
–19–
REV. A
ADI [ ADI ]
