AD9888
0F
3
COAST Input Polarity
The default setting is 15 and corresponds to a threshold
value of 0.16 V.
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
10
2
Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 9.
Table XX. COAST Input Polarity Settings
CSTPOL
Function
0
1
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue
operating at the same nominal frequency until COAST
goes HIGH.
Table XXIII. Red Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 9)
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue
operating at the same nominal frequency until COAST
goes LOW.
The default setting for this register is 0.
1 Blue Clamp Select
10
This function needs to be used along with the COAST
polarity override bit (Bit 4).
A bit that determines whether the blue channel is clamped
to ground or to midscale. Clamping to midscale actually
clamps to Pin 24.
The power-up default value is CSTPOL = 1.
0F
2
Seek Mode Override
Table XXIV. Blue Clamp Select Settings
This bit is used to either allow or disallow the low-power
mode. The low-power mode (seek mode) occurs when
there are no signals on any of the Sync inputs.
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 24)
Table XXI. Seek Mode Override Settings
The default setting for this register is 0.
Select
Result
11
7:0 Sync Separator Threshold
1
0
Allow Seek Mode
Disallow Seek Mode
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulsewidth. Note: the sync separator threshold uses an
internal dedicated clock with a frequency of approxi-
mately 5 MHz.
The default for this register is 1.
1 PWRDN
0F
This bit is used to put the chip in power-down mode. In this
mode the chip’s power dissipation is reduced to a fraction
of the typical power (see the Electrical Characteristics
table for exact power dissipation). When in power-down,
the HSOUT, VSOUT, DATACK, DATACK, and all 48
of the data outputs are put into a high impedance state.
(Note: the SOGOUT output is not put into high imped-
ance.) Circuit blocks that continue to be active during
power-down include the voltage references, sync process-
ing, sync detection, and the serial register. These blocks
facilitate a fast start-up from power-down.
The default for this register is 32.
12
13
7-0 Pre-COAST
This register allows the COAST signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
Table XXII. Power-Down Settings
7-0 Post-COAST
Select
Result
This register allows the COAST signal to be applied
following to the Vsync signal. This is necessary in cases
where post-equalization pulses are present. The step size
for this control is one Hsync period.
0
1
Power-Down
Normal Operation
The default for this register is 1.
The default is 0.
10
7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10 mV
and the maximum setting equaling 330 mV.
–23–
REV. A
ADI [ ADI ]
