AD9888
P0
P1
P2
P3
P4
P5
P6
P7
RGBIN
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
GOUTA
Y0
U0
Y1
V1
Y2
U2
Y3
V3
Y4
U4
ROUTA
HSOUT
VARIABLE DURATION
Figure 22. 4:2:2 Output Mode
2-WIRE SERIAL REGISTER MAP
The AD9888 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Table V. Control Register Map
Read and
Write or
Address Read Only Bits Value
Hex
Default
Register Name Function
00H
RO
7:0
Chip Revision
An 8-bit register which represents the silicon revision level. Revision 0
= 0000 0000.
01H
R/W
7:0
01101001 PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first whenever
a change is needed. (This will give the PLL more time to lock.) See Note
1.
02H
03H
R/W
R/W
7:4
7:2
1101**** PLL Div LSB
01****** VCO/CPMP
**001***
Bits [7:4] LSBs of the PLL divider word. See Note 1.
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the low-
pass filter. (See PLL description.)
04H
05H
R/W
R/W
7:3
7:0
10000*** Phase Adjust
ADC Clock phase adjustment. Larger values mean more delay. (1 LSB =
T/32)
00001000 Clamp Placement Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
06H
07H
R/W
R/W
7:0
7:0
00010100 Clamp Duration Number of clock periods that the Clamp signal is actively clamping.
00100000 Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000 Red Gain
Controls ADC input range (Contrast) of each respective channel. Bigger
values give less contrast.
09H
0AH
0BH
R/W
R/W
R/W
7:0
7:0
7:1
10000000 Green Gain
10000000 Blue Gain
1000000* Red Offset
Controls dc offset (Brightness) of each respective channel. Bigger values
decrease brightness.
0CH
0DH
R/W
R/W
7:1
7:1
1000000* Green Offset
1000000* Blue Offset
–17–
REV. A
ADI [ ADI ]
