AD9888
Table V. Control Register Map (continued)
Register Name Function
Read and
Write or
Address Read Only Bits Value
Hex
Default
0EH
R/W
7:0
0******* Sync Control
Bit 7—Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0Eh.)
*1******
Bit 6—Hsync Input Polarity. Indicates to the PLL the polarity of the incom-
ing Hsync signal. (Logic 0 = active low, Logic 1 = active high.)
**0*****
Bit 5—Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync).
***0****
Bit 4—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is selected
via Bit 6 in Register 14H.
****0***
Bit 3—Active Hsync select. Logic 0 selects Hsync as the active sync. Logic
1 selects Sync-on-Green as the active sync. Note: the indicated Hsync will
be used only if Bit 4 is set to Logic 1 or if both syncs are active (Bits 1, 7 =
Logic 1 in Register 14H).
*****0**
******0*
Bit 2—Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
Bit 1—Active Vsync override. If set to Logic 1, the user can select the Vsync
to be used via Bit 0. If set to Logic 0, the active interface is selected via Bit
3 in Register 14H.
*******0
0*******
Bit 0—Active Vsync select. Logic 0 selects Raw Vsync as the output Vsync.
Logic 1 selects Sync Separated Vsync as the output Vsync. Note: the indi-
cated Vsync will be used only if Bit 1 is set to Logic 1.
0FH
R/W
7:1
Bit 7—Clamp Function. Chooses between Hsync for Clamp signal or an-
other external signal to be used for clamping. (Logic 0 = Hsync, Logic 1 =
Clamp.)
*1******
**0*****
***0****
****1***
*****1**
******1*
Bit 6—Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
active high, Logic 1 selects active low.)
Bit 5—COAST select. Logic 0 selects the coast input pin to be used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 4—COAST Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in register 0Fh.)
Bit 3—COAST Polarity. Changes polarity of external COAST signal.
(Logic = 0 = active low, Logic 1 = active high.)
Bit 2—Seek Mode Override. (Logic 1 = allow low-power mode, Logic 0 =
disallow low-power mode.)
Bit 1—PWRDN. Full Chip Power Down, active low. (Logic 0 = Full Chip
Power Down, Logic 1 = normal.)
10H
11H
R/W
7:3
7:0
01111*** Sync-on-Green
Sync-on-Green Threshold – Sets the voltage level of the Sync-on-Green
slicer’s comparator.
Threshold
*****0**
******0*
*******0
Bit 2—Red Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 9).
Bit 1—Blue Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 24).
Bit 0—Must be set to 1 for proper operation.
R/W
00100000 Sync Separator
Threshold
Sync Separator Threshold – Sets how many internal 5 MHz clock periods the
sync separator will count to before toggling high or low. This should be set to
some number greater than the maximum Hsync or equalization pulsewidth.
12H
13H
R/W
R/W
7:0
7:0
00000000 Pre-COAST
00000000 Post-COAST
Pre-COAST – Sets the number of Hsync periods that coast becomes active
prior to Vsync.
Post-COAST – Sets the number of Hsync periods that coast stays active
following Vsync.
–18–
REV. A
ADI [ ADI ]
