AD9851
The function assignments of the data and control words are
shown in Tables I and III; the detailed timing sequence for
updating the output frequency and/or phase, resetting the de-
vice, engaging the 6× REFCLK Multiplier, and powering up/
down, are shown in the timing diagrams of Figures 13–20. As a
programming example for the following DDS characteristics:
1.
2.
3.
4.
Phase set to 11.25 degrees.
6× REFCLK Multiplier engaged.
Powered-up mode selected.
Output = 10 MHz (for 180 MHz system clock).
In parallel mode, user would program the 40-bit control word
(composed of five 8-bit loads) as follows:
W0
W1
W2
W3
W4
=
=
=
=
=
00001001
00001110
00111000
11100011
10001110
If in serial mode, load the 40 bits starting from the LSB location
of W4 in the above “array,” loading from right to left, and end-
ing with the MSB of W0.
Table I. 8-Bit Parallel-Load Data/Control Word Functional Assignment
Word
W0
W1
W2
W3
W4
Data[7]
Phase–b4 (MSB)
Freq–b31 (MSB)
Freq–b23
Freq–b15
Freq–b7
Data[6]
Phase–b3
Freq–b30
Freq–b22
Freq–b14
Freq–b6
Data[5]
Phase–b2
Freq–b29
Freq–b21
Freq–b13
Freq–b5
Data[4]
Phase–b1
Freq–b28
Freq–b20
Freq–b12
Freq–b4
Data[3]
Phase–b0 (LSB)
Freq–b27
Freq–b19
Freq–b11
Freq–b3
Data[2]
Power-Down
Freq–b26
Freq–b18
Freq–b10
Freq–b2
Data[1]
Logic 0*
Freq–b25
Freq–b17
Freq–b9
Freq–b1
Data[0]
6× REFCLK
Multiplier
Enable
Freq–b24
Freq–b16
Freq–b8
Freq–b0 (LSB)
*This bit is always Logic 0 unless invoking the serial mode (see Figure 17). After serial mode is entered, this data bit must be set back to Logic 0 for proper operation.
SYSCLK
t
CD
DATA
W0*
W1
W2
W3
W4
t
DS
W CLK
t
DH
t
WH
t
WL
t
FD
t
FL
FQ UD
t
FH
t
CF
A
OUT
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
AND IS ASYNCHRONOUS WITH REFERENCE CLOCK
VALID DATA
Figure 13. Parallel-Load Frequency/Phase Update Timing Sequence
Note: To update W0 it is not necessary to load W1 through W4. Simply load W0 and assert FQ_UD. To update W1, reload W0
then W1 . . . users do not have random access to programming words.
Table II. Timing Specifications
Symbol
t
DS
t
DH
t
WH
t
WL
t
CD
t
FH
t
FL
t
FD
t
CF
Definition
Data Setup Time
Data Hold Time
W_CLK High
W_CLK Low
REFCLK Delay after FQ_UD
FQ_UD High
FQ_UD Low
FQ_UD Delay after W_CLK
Output Latency from FQ_UD
Frequency Change
Phase Change
Min
3.5 ns
3.5 ns
3.5 ns
3.5 ns
3.5 ns*
7.0 ns
7.0 ns
7.0 ns
18 SYSCLK Cycles
13 SYSCLK Cycles
*Specification does not apply when the 6× REFCLK Multiplier is engaged.
–10–
REV. C
AD [ ANALOG DEVICES ]
