AD9851
Rx
RF IN
VCA
ADC CLOCK FREQUENCY
LOCKED TO
Tx CHIP/SYMBOL/PN RATE
180MHz
OR 30MHz
REFERENCE
CLOCK
AGC
ADC ENCODE
I/Q MIXER
AND
LOW PASS
FILTER
I
8
AD9059
Q
DUAL
8-BIT ADC
8
DIGITAL
DEMODULATOR
Rx BASEBAND
DIGITAL DATA OUT
AD9851
CLOCK
GENERATOR
32
CHIP/SYMBOL/PN
RATE DATA
Figure 1. “Chip Rate” Clock Generator Application in a Spread Spectrum Receiver
IOUT
MICROPROCESSOR
OR
MICROCONTROLLER
DATA
BUS
8-BIT PARALLEL DATA,
OR 1-BIT 40 SERIAL DATA,
RESET, W CLK AND FQ UD
IOUTB
470pF
100k
100k
100
200
LOW-PASS
FILTER
200
7TH ORDER ELLIPTICAL
70MHz LOW PASS
200 IMPEDANCE
VOLTAGE HERE = CENTER POINT
OF SINE WAVE (0.5V TYPICALLY)
USING PASSIVE "AVERAGING" CIRCUIT
0 TO 1V p-p
SINE WAVE
AD9851
180MHz OR 30MHz
REFERENCE
CLOCK
R
SET
3.9k
CMOS
OUTPUTS
QOUT
QOUTB
Figure 2. Basic Clock Generator Configuration
Both IOUT and IOUTB are equally loaded with 100
Ω.
Two
100 kΩ resistors “sample” each output and average the two
voltages. The result is filtered with the 470 pF capacitor and
applied to one comparator input as a dc switching threshold.
The filtered DAC sine wave output is applied to the other com-
parator input. The comparator will toggle with nearly 50% duty
cycle as the sine wave alternately traverses the “center point”
threshold.
IF FREQUENCY
IN
FILTER
RF
FREQUENCY
OUT
REFERENCE
CLOCK
PHASE
COMPARATOR
FILTER
LOOP
FILTER
VCO
RF
FREQUENCY
OUT
AD9851
DDS
REF CLK IN
TUNING
WORD
PROGRAMMABLE
"DIVIDE-BY-N" FUNCTION
(WHERE N = 2
32
/TUNING WORD)
Figure 5. Digitally-Programmable “Divide-by-N” Function
in PLL
AD9851/FSPCB
EVALUATION
BOARD
DAC
OUT
FILTER
REFERENCE
CLOCK
8-BIT
DATA
BUS
AD9851
DDS
TUNING
WORD
EZ-KIT LITE
DSP
ADSP-2181
DSP
PROCESSOR
ADSP-2181
BUS
Figure 3. Frequency/Phase-Agile Local Oscillator for
Frequency Mixing/Multiplying
REFERENCE
CLOCK
INPUT/
OUTPUT
DECODE
LOGIC
AD9851
DDS
REF
OSC
FM RF
OUTPUT
AD1847
L&R
AUDIO IN STEREO
CODEC
AD9851
DDS
TUNING
WORD
Figure 6. High Quality, All-Digital RF Frequency Modulation
FILTER
PHASE
COMPARATOR
LOOP
FILTER
VCO
RF
FREQUENCY
OUT
DIVIDE-BY-N
High quality, all digital RF frequency modulation generation
with the ADSP-2181 DSP and the AD9851 DDS. This applica-
tion is well documented in Analog Devices’ application Note
AN-543, and uses an “image” of the DDS output as illustrated
in Figure 8.
Figure 4. Frequency/Phase-Agile Reference for PLL
–6–
REV. C
AD [ ANALOG DEVICES ]
