AD9851
DATA
W0
W1
W2
W3
W39
FQ UD
W CLK
40 W CLK CYCLES
Figure 19. Serial-Load Frequency/Phase Update Sequence
Table III. 40-Bit Serial-Load Word Functional Assignment
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
Freq–b0 (LSB)
Freq–b1
Freq–b2
Freq–b3
Freq–b4
Freq–b5
Freq–b6
Freq–b7
Freq–b8
Freq–b9
Freq–b10
Freq–b11
Freq–b12
*This bit is always Logic 0.
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
Freq–b13
Freq–b14
Freq–b15
Freq–b16
Freq–b17
Freq–b18
Freq–b19
Freq–b20
Freq–b21
Freq–b22
Freq–b23
Freq–b24
Freq–b25
Freq–b26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
Freq–b27
Freq–b28
Freq–b29
Freq–b30
Freq–b31 (MSB)
6× REFCLK Multi-
plier Enable
Logic 0*
Power-Down
Phase–b0 (LSB)
Phase–b1
Phase–b2
Phase–b3
Phase–b4 (MSB)
Figure 20 shows a normal 40-bit serial word load sequence with
W33 always set to Logic 0 and W34 set to Logic 1 or Logic 0 to
control the power-down function. The logic states of the remain-
ing 38 bits are unimportant and are marked with an X, indicating
“don’t care” status. To power down, set W34 = 1. To power up
from a powered down state, change W34 to Logic 0. Wake-up
from power-down mode requires approximately 5
µs.
Note: The 40-bit input register of the AD9851 is fully program-
mable while in the power-down mode.
DATA (7) –
W0 = X
W33 = 0 W34 = 1 W35 = X W38 = X W39 = X
OR 0
FQ UD
W CLK
40 W_CLK RISING EDGES
Figure 20. Serial-Load Power-Down\Power-Up Sequence
V
DD
V
DD
V
DD
V
DD
DIGITAL
OUT
VINP/
VINN
DIGITAL
IN
IOUT
IOUTB
a. DAC Output
b. Comparator Output
c. Comparator Input
d. Digital Input
Figure 21. I/O Equivalent Circuits
–12–
REV. C
AD [ ANALOG DEVICES ]
