AD9851
SYSCLK
t
RH
RESET
t
RL
t
RR
t
RS
t
OL
A
OUT
SYMBOL
DEFINITION
CLK DELAY AFTER RESET RISING EDGE
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
COS (0 )
MIN SPEC
3.5ns*
3.5ns*
2 SYSCLK CYCLES
5 SYSCLK CYCLES
13 SYSCLK CYCLES
t
RH
t
RL
t
RR
t
RS
t
OL
*
SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
Figure 14. Master Reset Timing Sequence
Results of Reset, Figure 14
– Phase Accumulator zeroed such that the output = 0 Hertz
(dc).
– Phase Offset register set to zero such that DAC IOUT = Full-
Scale output and IOUTB = zero mA output.
– Internal Programming Address pointer reset to W0.
– Power-down bit reset to “0” (power-down disabled).
– 40-bit Data Input Register is NOT cleared.
– 6× Reference Clock multiplier is disabled.
– Parallel programming mode selected by default.
DATA (W0)
XXXXX10X
Entry to the serial mode, Figure 17, is via the parallel mode
which is selected by default after a RESET is asserted. One
needs only to program the first eight bits (word W0) with the
sequence xxxxx011 as shown in Figure 17 to change from paral-
lel to serial mode. The W0 programming word may be sent over
the 8-bit data bus or hardwired as shown in Figure 18. After
serial mode is achieved, the user must follow the programming
sequence of Figure 19.
DATA (W0)
XXXXX011
W CLK
W CLK
FQ UD
ENABLE
SERIAL MODE
FQ UD
SYSCLK
DAC
STROBE
INTERNAL CLOCKS
DISABLED
Figure 17. Serial-Load Enable Sequence
Figure 15. Parallel-Load Power-Down Sequence/Internal
Operation
DATA (W0)
XXXXX00X
Note: After serial mode is invoked, it is best to immediately
write a valid 40-bit serial word (see Figure 19), even if it is all
zeros, followed by a FQ_UD rising edge to flush the “residual”
data left in the DDS core. A valid 40-bit serial word is any word
where W33 is Logic 0.
D3
D2
D4
28
D5
27
1
2
AD9851
W CLK
+V
SUPPLY
10k
3
4
D1
D0
D6
26
D7
25
FQ UD
SYSCLK
INTERNAL CLOCKS
ENABLED
Figure 18. Hardwired xxxxx011 Configuration for Serial-
Load Enable Word W0 in Figure 17
Figure 16. Parallel-Load Power-Up Sequence (to Recover
from Power-Down)/Internal Operation
REV. C
–11–
AD [ ANALOG DEVICES ]
