AD9850
IF
FREQUENCY
IN
RF
5-POLE ELLIPTICAL
42MHz LOW-PASS
200⍀ IMPEDANCE
FILTER
FREQUENCY
OUT
GND
+V
S
LOW-PASS
FILTER
IOUT
FILTER
125MHz
200⍀
100k⍀
100k⍀
RESET, AND 2
AD9850
TUNING
WORD
DATA
BUS
470pF
COMPLETE DDS
PROCESSOR
CLOCK LINES
REFERENCE
100⍀
3a. Frequency/Phase–Agile Local Oscillator
IOUTB
AD9850
VINN
XTAL
OSC
CLK
VINP
QOUT
QOUTB
RF
200⍀
125MHz
FREQUENCY
OUT
VCO
CMOS
CLOCK
AD9850
COMPLETE
DDS
FILTER
PHASE
LOOP
OUTPUTS
COMPARATOR FILTER
REFERENCE
CLOCK
RSET
COMP
TRUE
DIVIDE-BY-N
TUNING
WORD
Figure 1. Basic AD9850 Clock Generator Application
with Low-Pass Filter
3b. Frequency/Phase–Agile Reference for PLL
REF
RF
FREQUENCY
FREQUENCY
I
8
8
Rx
I/Q MIXER
AND
LOW-PASS
FILTER
BASEBAND
DIGITAL
DATA
AD9059
DUAL 8-BIT
ADC
OUT
DIGITAL
DEMODULATOR
PHASE
LOOP
FILTER
Rx
IF IN
VCO
Q
COMPARATOR
OUT
PROGRAMMABLE
DIVIDE-BY-N
FUNCTION
FILTER
AGC
VCA
ADC CLOCK
FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL PN RATE
AD9850
COMPLETE
DDS
ADC ENCODE
125MHz
AD9850
CLOCK
GENERATOR
32
TUNING WORD
CHIP/SYMBOL/PN
RATE DATA
REFERENCE
CLOCK
3c. Digitally-Programmable Divide-by-N Function in PLL
Figure 2. AD9850 Clock Generator Application in a
Spread-Spectrum Receiver
Figure 3. AD9850 Complete DDS Synthesizer in
Frequency Up-Conversion Applications
THEORY OF OPERATION AND APPLICATION
The frequency tuning word sets the modulus of the counter,
which effectively determines the size of the increment (∆ Phase)
that is added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the
accumulator overflows, which results in a higher output fre-
quency. The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850. The
relationship of the output frequency, reference clock, and tuning
word of the AD9850 is determined by the formula
The AD9850 uses direct digital synthesis (DDS) technology, in the
form of a numerically controlled oscillator, to generate a frequency/
phase-agile sine wave. The digital sine wave is converted to analog
form via an internal 10-bit high speed D/A converter, and an
on-board high speed comparator is provided to translate the analog
sine wave into a low jitter TTL/CMOS compatible output square
wave. DDS technology is an innovative circuit architecture that
allows fast and precise manipulation of its output frequency under
full digital control. DDS also enables very high resolution in the
incremental selection of output frequency; the AD9850 allows an
output frequency resolution of 0.0291 Hz with a 125 MHz refer-
ence clock applied. The AD9850’s output waveform is phase con-
tinuous when changed.
f
OUT = (∆ Phase × CLKIN)/232
The basic functional block diagram and signal flow of the
AD9850 configured as a clock generator is shown in Figure 4.
where:
∆Phase is the value of the 32-bit tuning word.
CLKIN is the input reference clock frequency in MHz.
fOUT is the frequency of the output signal in MHz.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the reference clock divided by the 2N number of bits in the
tuning word. The phase accumulator is a variable-modulus
counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows, it wraps
around, making the phase accumulator’s output contiguous.
The digital sine wave output of the DDS block drives the inter-
nal high speed 10-bit D/A converter that reconstructs the sine
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy as manifested in the low
jitter performance of the AD9850. Because the output of the
REV. H
–8–
ADI [ ADI ]
