AD9850
PIN CONFIGURATION
1
2
D4
D3
D2
28
27
D5
3
D1
D6
26
25
LSB D0
DGND
DVDD
W CLK
4
D7 MSB/SERIAL LOAD
5
24
23
DGND
DVDD
RESET
6
AD9850
7
22
TOP VIEW
8
21 IOUT
FQ UD
CLKIN
AGND
AVDD
(Not to Scale)
20
9
IOUTB
10
11
12
13
14
AGND
19
18
AVDD
R
DACBL (NC)
17
16
SET
QOUTB
QOUT
VINP
VINN
15
NC = NO CONNECT
Table I. PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
4 to 1,
28 to 25
D0 to D7
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word.
5, 24
6, 23
7
DGND
DVDD
W_CLK
FQ_UD
Digital Ground. These are the ground return leads for the digital circuitry.
Supply Voltage Leads for Digital Circuitry.
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8
Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase)
loaded in the data input register; it then resets the pointer to Word 0.
9
CLKIN
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19
11, 18
12
AGND
AVDD
RSET
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
Supply Voltage for the Analog Circuitry (DAC and Comparator).
DAC’s External RSET Connection. This resistor value sets the DAC full-scale output current. For
normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 kΩ connected to ground. The RSET/IOUT
relationship is IOUT = 32 (1.248 V/RSET).
13
14
15
16
17
QOUTB
QOUT
VINN
Output Complement. This is the comparator’s complement output.
Output True. This is the comparator’s true output.
Inverting Voltage Input. This is the comparator’s negative input.
Noninverting Voltage Input. This is the comparator’s positive input.
VINP
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a no connect for optimum performance.
20
21
22
IOUTB
IOUT
Complementary Analog Output of the DAC.
Analog Current Output of the DAC.
RESET
Reset. This is the master reset function; when set high, it clears all registers (except the input register), and
the DAC output goes to cosine 0 after additional clock cycles—see Figure 7.
REV. H
–5–
ADI [ ADI ]
