AD9850
CLKIN
RESET
tRL
tRH
tRR
tRS
tOL
COS (0)
COS OUT
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED.
SYMBOL DEFINITION
MINIMUM
3.5ns
tRH
tRL
tRR
tRS
tOL
CLK DELAY AFTER RESET RISING EDGE
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
3.5ns
2 CLK CYCLES
5 CLK CYCLES
13 CLK CYCLES
RESET OUTPUT LATENCY
RESULTS OF RESET:
– FREQUENCY/PHASE REGISTER SET TO 0
– ADDRESS POINTER RESET TO W0
– POWER-DOWN BIT RESET TO 0
– DATA INPUT REGISTER UNEFFECTED
Figure 7. Master Reset Timing Sequence
XXXXX100
DATA (W0)
W CLK
FQ UD
CLKIN
DAC STROBE
INTERNAL CLOCKS DISABLED
Figure 8. Parallel Load Power-Down Sequence/Internal Operation
DATA (W0)
XXXXX000
W CLK
FQ UD
CLKIN
INTERNAL CLOCKS ENABLED
Figure 9. Parallel Load Power-Up Sequence/Internal Operation
REV. H
–11–
ADI [ ADI ]
