AD9832
PIN FUNCTION DESCRIPTIONS
Pin #
Mnemonic
Function
ANALOG SIGNAL AND REFERENCE
1
FS ADJUST
Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This determines
the magnitude of the full-scale DAC current. The relationship between R
SET
and the full-scale current is
as follows:
IOUT
FULL-SCALE
= 12.5
×
V
REFIN
/R
SET
V
REFIN
= 1.21
V nominal, R
SET
= 3.9 kΩ
typical
2
REFIN
Voltage Reference Input. The AD9832 can be used with either the onboard reference, which is available
from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.
The AD9832 accepts a reference of 1.21 V nominal.
3
REFOUT
Voltage Reference Output. The AD9832 has an onboard reference of value 1.21 V nominal. The refer-
ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con-
necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
14
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between
IOUT and AGND.
16
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling
ceramic capacitor should be connected between COMP and AVDD.
POWER SUPPLY
4
DVDD
5
13
15
DGND
AGND
AVDD
Positive Power Supply for the Digital Section. A 0.1
µF
decoupling capacitor should be connected be-
tween DVDD and DGND. DVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
Digital Ground.
Analog Ground.
Positive Power Supply for the Analog Section. A 0.1
µF
decoupling capacitor should be connected be-
tween AVDD and AGND. AVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
DIGITAL INTERFACE AND CONTROL
6
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.
The output frequency accuracy and phase noise are determined by this clock.
7
SCLK
Serial Clock, Logic Input. Data is clocked into the AD9832 on each falling SCLK edge.
8
SDATA
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
9
FSYNC
Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed
that a new word is being loaded into the device.
10
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the
phase accumulator. The frequency register to be used can be selected using the pin FSELECT or the bit
FSELECT. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state
when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an
uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid
any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. When the bit is
being used to select the frequency register, the pin FSELECT should be tied to DGND.
11, 12 PSEL0, PSEL1 Phase Select Input. The AD9832 has four phase registers. These registers can be used to alter the value
being input to the SIN ROM. The contents of the phase register are added to the phase accumulator out-
put, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register
to be used can be selected using the bits PSEL0 and PSEL1. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK
rising edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the
selected phase register. When the phase registers are being controlled by the bits PSEL0 and PSEL1, the
pins should be tied to DGND.
REV. A
–5–
AD [ ANALOG DEVICES ]
