AD9832
TIMING CHARACTERISTICS
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
11A
*
Limit at
T
MIN
to T
MAX
(B Version)
40
16
16
50
20
20
15
20
SCLK – 5
15
5
8
8
DD
= +3.3 V
10%; +5 V
10%; AGND = DGND = 0 V, unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
SCLK Period
SCLK High Duration
SCLK Low Duration
FSYNC to SCLK Falling Edge Setup Time
FSYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
*See Pin Function Descriptions.
Guaranteed by design but not production tested.
t
1
MCLK
t
2
t
3
Figure 2. Master Clock
t
5
SCLK
t
4
t
7
FSYNC
t
6
t
8
t
10
t
9
SDATA
D15
D14
D2
D1
D0
D15
D14
Figure 3. Serial Timing
MCLK
t
11
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
t
11A
VALID DATA
Figure 4. Control Timing
REV. A
–3–
AD [ ANALOG DEVICES ]
