AD9832
Table V. Commands
Table VI. Controlling the AD9832
C3
0
0
0
C2
0
0
0
C1
0
0
1
C0
0
1
0
Command
Write 16 phase bits (Present 8 Bits + 8 Bits
in Defer Register) to Selected PHASE REG.
Write 8 phase bits to Defer Register.
Write 16 frequency bits (Present 8 Bits
+ 8 Bits in Defer Register) to Selected
FREQ REG.
Write 8 frequency bits to Defer Register.
Bits D9 (PSEL0) and D10 (PSEL1) are
used to Select the PHASE REG when
SELSRC = 1. When SELSRC = 0, the
PHASE REG is Selected using the pins
PSEL0 and PSEL1.
Bit D11 is used to Select the FREQ REG
when SELSRC = 1. When SELSRC = 0,
the FREQ REG is Selected using the pin
FSELECT.
To control the PSEL0, PSEL1 and
FSELECT bits using only one write, this
command is used. Bits D9 and D10 are
used to Select the PHASE REG and Bit
11 is used to Select the FREQ REG when
SELSRC = 1. When SELSRC = 0, the
PHASE REG is Selected using the pins
PSEL0 and PSEL1 and the FREQ REG
is Selected using the pin FSELECT.
Reserved. Configures the AD9832 for
Test Purposes.
D15 D14 Command
1
0
Selects source of Control for the PHASE and FREQ
Registers and Enables Synchronization.
Bit D13 is the SYNC Bit. When this bit is High,
reading of the FSELECT, PSEL0 and PSEL1 bits/
pins and the loading of the Destination Register with
data is synchronized with the rising edge of MCLK.
The latency is increased by 2 MCLK cycles when
SYNC = 1. When SYNC = 0, the loading of the
data and the sampling of FSELECT/PSEL0/PSEL1
occurs asynchronously.
Bit D12 is the Select Source Bit (SELSRC). When
this bit Equals 1, the PHASE/FREQ REG is
Selected using the bits FSELECT, PSEL0 and
PSEL1. When SELSRC = 0, the PHASE/FREQ
REG is Selected using the pins FSELECT, PSEL0
and PSEL1.
Sleep, Reset and Clear.
D13 is the SLEEP bit. When this bit equals 1, the
AD9832 is powered down, internal clocks are
disabled and the DAC’s current sources and
REFOUT are turned off. When SLEEP = 0, the
AD9832 is powered up. When RESET (D12) = 1,
the phase accumulator is set to zero phase which
corresponds to an analog output of midscale. When
CLR (D11) = 1, SYNC and SELSRC are set to
zero. CLR resets to 0 automatically.
0
0
0
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
Table VII. Writing to the AD9832 Data Registers
D15
C3
D14
C2
D13
C1
D12
C0
D11
A3
D10
A2
D9
A1
D8
A0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
Table VIII. Setting SYNC and SELSRC
D15
1
D14
0
D13
D12
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
SYNC SELSRC
Table IX. Power-Down, Resetting and Clearing the AD9832
D15
1
D14
1
D13
D12
D11
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
SLEEP RESET CLR
REV. A
–9–
AD [ ANALOG DEVICES ]
