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AD9832BRU 参数 Datasheet PDF下载

AD9832BRU图片预览
型号: AD9832BRU
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS DDS完成 [CMOS Complete DDS]
分类和应用: 数据分配系统
文件页数/大小: 16 页 / 149 K
品牌: AD [ ANALOG DEVICES ]
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AD9832–SPECIFICATIONS
Parameter
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (f
MAX
)
I
OUT
Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)
3
Narrow Band (± 50 kHz)
Wide Band (± 2 MHz)
Clock Feedthrough
Wake-Up Time
4
Power-Down Option
VOLTAGE REFERENCE
Internal Reference @ +25°C
T
MIN
to T
MAX
REFIN Input Impedance
Reference TC
REFOUT Output Impedance
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
I
AA
I
DD
I
AA
+ I
DD5
Low Power Sleep Mode
1
(V
DD
= +3.3 V 10%; +5 V 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; REFIN =
REFOUT; R
SET
= 3.9 k ; R
LOAD
= 300 for IOUT unless otherwise noted)
Units
Bits
MSPS nom
mA nom
mA max
V max
LSB typ
LSB typ
Test Conditions/Comments
AD9832B
10
25
4
4.5
1.35
±
1
±
0.5
3 V Power Supply
50
–53
–72
–70
–50
–60
1
Yes
1.21
1.21
±
7%
10
100
300
V
DD
– 0.9
0.9
10
10
2.97/5.5
2.97/5.5
5
2.5 + 0.4/MHz
15
24
350
dB min
dBc max
dBc min
dBc min
dBc min
dBc typ
ms typ
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
5 V Power Supply
3 V Power Supply
Volts typ
Volts min/max
MΩ typ
ppm/°C typ
typ
V min
V max
µA
max
pF max
V min/V max
V min/V max
mA max
mA typ
mA max
mA max
µA
max
5 V Power Supply
5 V Power Supply
3 V Power Supply
5 V Power Supply
NOTES
1
Operating temperature range is as follows: B Version, –40
°C
to +85°C.
2
100% production tested.
3
f
MCLK
= 6.25 MHz, Frequency Word = 5671C71C HEX, f
OUT
= 2.11 MHz.
4
See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
The AD9832 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated.
For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
R
SET
3.9kΩ
10nF
REFOUT
REFIN
FS
ADJUST
COMP
AVDD
10nF
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
12
SIN
ROM
10-BIT DAC
IOUT
300Ω
50pF
AD9832
Figure 1. Test Circuit with Which Specifications Are Tested
–2–
REV. A