AD9826
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (I
OH
= 50
µA)
Low Level Output Voltage (I
OL
= 50
µA)
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
C
L
= 10 pF, unless otherwise noted.)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
I
OH
I
OL
V
OH
V
OL
Min
2.0
0.8
10
10
10
4.5
0.1
50
50
2.95
0.05
Typ
Max
Unit
V
V
µA
µA
pF
V
V
µA
µA
V
V
TIMING SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
Symbol
t
PRA
t
PRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2ADR
t
C2ADF
t
C2C1
t
AD
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
t
OD
t
DV
t
HZ
Min
200
80
30
8
8
0
0
5
30
5
2
10
10
10
10
10
10
6
10
10
3 (Fixed)
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUTS
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
REV. A
–3–
AD [ ANALOG DEVICES ]
