AD9826
TIMING DIAGRAMS
ANALOG
INPUTS
t
AD
PIXEL n (R,G,B)
t
AD
PIXEL
(n+1)
PIXEL
(n+2)
t
C1
t
C2C1
t
PRA
CDSCLK1
t
C1C2
CDSCLK2
t
C2
t
C2ADF
t
ADCLK
ADCCLK
t
ADC2
t
C2ADR
t
ADCLK
OUTPUT
DATA
D<7:0>
R(n–2)
G(n–2)
HIGH
BYTE
G(n–2)
LOW
BYTE
B(n–2)
HB
B(n–2)
LB
R(n–1)
HB
R(n–1)
LB
t
OD
G(n–1)
HB
G(n–1)
LB
B(n–1)
HB
B(n–1)
LB
R(n)
HB
R(n)
LB
G(n)
HB
G(n)
LB
Figure 1. 3-Channel CDS Mode Timing
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
ANALOG
INPUTS
t
AD
PIXEL n
PIXEL
(n+1)
t
AD
PIXEL
(n+2)
t
C1
t
C2C1
t
PRB
CDSCLK1
t
C1C2
t
C2
CDSCLK2
t
C2ADR
t
C2ADF
ADCCLK
t
ADCLK
OUTPUT
DATA
D<7:0>
PIXEL (n–4)
HIGH BYTE
PIXEL (n–4)
LOW BYTE
PIXEL (n–3)
HIGH BYTE
t
ADCLK
t
OD
PIXEL (n–3)
LOW BYTE
PIXEL (n–2)
HIGH BYTE
PIXEL (n–2)
LOW BYTE
NOTE
IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
Figure 2. 1-Channel CDS Mode Timing
–8–
REV. A
AD [ ANALOG DEVICES ]
