AD9826
ANALOG
INPUTS
t
AD
PIXEL n
t
AD
t
C1
t
C2C1
PIXEL (n+1)
PIXEL (n+2)
t
PRA
CDSCLK1
t
C1C2
t
C2
CDSCLK2
t
C2ADR
t
ADC2
ADCCLK
t
ADCLK
OUTPUT
DATA
D<7:0>
CH1(n–2)
HIGH
BYTE
LOW
BYTE
t
ADCLK
CH2(n–2)
HIGH
BYTE
LOW
BYTE
CH1(n–1)
HIGH
BYTE
LOW
BYTE
CH2(n–1)
HIGH
BYTE
LOW
BYTE
CH1(n)
HIGH
BYTE
LOW
BYTE
t
C2ADF
Figure 3. 2-Channel CDS Mode Timing
PIXEL
(n+1)
t
AD
t
C2
PIXEL n
ANALOG
INPUTS
CDSCLK2
t
C2ADR
t
ADC2
ADCCLK
t
C2ADF
t
ADCLK
OUTPUT
DATA
D<7:0>
CH1(n–2)
HIGH
BYTE
LOW
BYTE
t
ADCLK
CH2(n–2)
HIGH
BYTE
LOW
BYTE
CH1(n–1)
HIGH
BYTE
LOW
BYTE
CH2(n–1)
HIGH
BYTE
LOW
BYTE
CH1(n)
HIGH
BYTE
LOW
BYTE
Figure 4. 2-Channel SHA Mode Timing
REV. A
–9–