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AD9767ASTZRL 参数 Datasheet PDF下载

AD9767ASTZRL图片预览
型号: AD9767ASTZRL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位/ 12位/ 14位, 125 MSPS双通道TxDAC数字 - 模拟转换器 [10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters]
分类和应用: 转换器数模转换器
文件页数/大小: 44 页 / 643 K
品牌: ADI [ ADI ]
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Data Sheet  
AD9763/AD9765/AD9767  
The gain drift temperature performance for a single-ended  
(VOUTA and VOUTB) or differential output (VDIFF) of the  
AD9763/AD9765/AD9767 can be enhanced by selecting  
temperature tracking resistors for RLOAD and RSET due to their  
ratiometric relationship.  
DAC TRANSFER FUNCTION  
Both DACs in the AD9763/AD9765/AD9767 provide comple-  
mentary current outputs, IOUTA and IOUTB. IOUTA provides a near  
full-scale current output (IOUTFS) when all bits are high (that is,  
DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/  
AD9767, respectively), while IOUTB, the complementary output,  
provides no current. The current output appearing at IOUTA and  
ANALOG OUTPUTS  
The complementary current outputs, IOUTA and IOUTB, in each  
DAC can be configured for single-ended or differential  
operation. IOUTA and IOUTB can be converted into complementary  
single-ended voltage outputs, VOUTA and VOUTB, via a load  
resistor (RLOAD) as described in Equation 5 through Equation 7.  
The differential voltage (VDIFF) existing between VOUTA and VOUTB  
can be converted to a single-ended voltage via a transformer or  
differential amplifier configuration. The ac performance of the  
AD9763/AD9765/AD9767 is optimum and specified using a  
differential transformer-coupled output in which the voltage  
swing at IOUTA and IOUTB is limited to 0.5 V. If a single-ended  
unipolar output is desired, select IOUTA.  
I
OUTB is a function of both the input code and IOUTFS. IOUTA for the  
AD9763, AD9765, and AD9767, respectively, can be expressed as  
IOUTA = (DAC CODE/1024) × IOUTFS  
IOUTA = (DAC CODE/4096) × IOUTFS  
IOUTA = (DAC CODE/16,384) × IOUTFS  
(1)  
IOUTB for the AD9763, AD9765, and AD9767, respectively, can be  
expressed as  
I
I
I
OUTB = ((1023 − DAC CODE)/1024) × IOUTFS  
OUTB = ((4095 − DAC CODE)/4096) × IOUTFS  
OUTB = ((16,383 − DAC CODE)/16,384) × IOUTFS  
(2)  
The distortion and noise performance of the AD9763/AD9765/  
AD9767 can be enhanced when it is configured for differential  
operation. The common-mode error sources of both IOUTA and  
where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal  
representation).  
IOUTB can be significantly reduced by the common-mode rejection  
IOUTFS is a function of the reference current (IREF). This is nominally  
of a transformer or differential amplifier. These common-mode  
error sources include even-order distortion products and noise.  
The enhancement in distortion performance becomes more  
significant as the frequency content of the reconstructed waveform  
increases. This is due to the first-order cancellation of various  
dynamic common-mode distortion mechanisms, digital feed-  
through, and noise.  
set by a reference voltage (VREFIO) and an external resistor (RSET).  
It can be expressed as  
I
OUTFS = 32 × IREF  
(3)  
where IREF is set as discussed in the Setting the Full-Scale  
Current section.  
The two current outputs typically drive a resistive load directly  
or via a transformer. If dc coupling is required, IOUTA and IOUTB  
should be directly connected to matching resistive loads (RLOAD  
that are tied to the analog common (ACOM). Note that RLOAD  
Performing a differential-to-single-ended conversion via a trans-  
former also provides the ability to deliver twice the reconstructed  
signal power to the load, assuming no source termination. Because  
the output currents of IOUTA and IOUTB are complementary, they  
become additive when processed differentially. A properly selected  
transformer allows the AD9763/AD9765/AD9767 to provide the  
required power and voltage levels to different loads.  
)
can represent the equivalent load resistance seen by IOUTA or IOUTB  
,
as is the case in a doubly terminated 50 ꢀ or 75 ꢀ cable. The single-  
ended voltage output appearing at the IOUTA and IOUTB nodes is  
V
V
OUTA = IOUTA × RLOAD  
OUTB = IOUTB × RLOAD  
(5)  
(6)  
The output impedance of IOUTA and IOUTB is determined by the  
equivalent parallel combination of the PMOS switches associated  
with the current sources and is typically 100 kꢀ in parallel with  
5 pF. It is also slightly dependent on the output voltage (that is,  
Note that the full-scale value of VOUTA and VOUTB must not  
exceed the specified output compliance range to maintain the  
specified distortion and linearity performance.  
VOUTA and VOUTB) due to the nature of a PMOS device. As a result,  
V
DIFF = (IOUTA IOUTB) × RLOAD  
(7)  
maintaining IOUTA and/or IOUTB at a virtual ground via an I-V  
op amp configuration results in the optimum dc linearity. Note that  
the INL/DNL specifications for the AD9763/AD9765/AD9767 are  
measured with IOUTA maintained at a virtual ground via an op amp.  
Equation 7 highlights some of the advantages of operating the  
AD9763/AD9765/AD9767 differentially. First, the differential  
operation helps cancel common-mode error sources associated  
with IOUTA and IOUTB such as noise, distortion, and dc offsets.  
Second, the differential code-dependent current and subsequent  
voltage, VDIFF, is twice the value of the single-ended voltage  
output (that is, VOUTA or VOUTB), thus providing twice the signal  
power to the load.  
Rev. G | Page 23 of 44