Data Sheet
AD9763/AD9765/AD9767
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
SLEEP
AVDD
Mini-Circuits
T1-1T
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
CLK
DIVIDER
FSADJ1
PMOS
CURRENT
SOURCE
ARRAY
I
I
OUTA1
OUTB1
R
1
SET
2kΩ
SEGMENTED
SWITCHES FOR
DAC1
REFIO
ANALYZER
LSB
SWITCH
DAC1
LATCH
0.1µF
PMOS
CURRENT
SOURCE
ARRAY
50Ω
50Ω
I
I
OUTA2
OUTB2
FSADJ2
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
R
2
DAC2
LATCH
SET
2kΩ
AD9763/
AD9765/
AD9767
MODE
MULTIPLEXING LOGIC
1.2V REF
DVDD1/
DVDD2
5V
WRT1/
IQWRT
DCOM1/
CHANNEL 1 LATCH
CHANNEL 2 LATCH
PORT 2
GAINCTRL
DCOM2 ACOM
PORT 1
WRT2/
IQSEL
DVDD1/DVDD2
DCOM1/DCOM2
50Ω
DIGITAL
DATA
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
TEKTRONIX
AWG2021
w/OPTION 4
Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,
Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
SLEEP
V
= V
A – V
V
B
ACOM
DIFF
OUT
OUT
CLK
R
2kΩ
1
SET
DIVIDER
FSADJ1
REFIO
PMOS
CURRENT
SOURCE
ARRAY
V
1A
I
OUT
OUTA1
I
1
REF
0.1µF
SEGMENTED
SWITCHES FOR
DAC1
LSB
1B
I
OUT
R 1A
L
50Ω
OUTB1
SWITCH
DAC1
LATCH
R 1B
L
50Ω
PMOS
CURRENT
SOURCE
ARRAY
V
2A
OUT
R
2
I
SET
OUTA2
2kΩ
FSADJ2
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
V
2B
R 2A
L
50Ω
I
OUT
OUTB2
I
2
DAC2
LATCH
REF
R 2B
L
50Ω
AD9763/
AD9765/
AD9767
MODE
MULTIPLEXING LOGIC
1.2V REF
DVDD1/
DVDD2
5V
DCOM1/
DCOM2
CHANNEL 1 LATCH
CHANNEL 2 LATCH
GAINCTRL
WRT1/
IQWRT
PORT 1
PORT 2
WRT2/
IQSEL
DIGITAL DATA INPUTS
NOTES
1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE R
= 2kΩ.
SET
Figure 58. Simplified Block Diagram
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
FUNCTIONAL DESCRIPTION
Figure 58 shows a simplified block diagram of the AD9763/
AD9765/AD9767. The AD9763/AD9765/AD9767 consist of
two DACs, each one with its own independent digital control
logic and full-scale output current control. Each DAC contains
a PMOS current source array capable of providing up to 20 mA
of full-scale current (IOUTFS).
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16thof an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kꢀ).
Rev. G | Page 21 of 44
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