AD8113
PIN FUNCTION DESCRIPTIONS
Mnemonic
INxx
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
SER/PAR
OUTyy
AGND
DV
CC
DGND
AV
EE
AV
CC
AV
CC
xx/yy
AV
EE
xx/yy
A0
A1
A2
A3
D0
D1
D2
D3
D4
NC
Pin Numbers
58, 60, 62, 64, 66, 68, 70, 72,
4, 6, 8, 10, 12, 14, 16, 18
96
97
98
95
100
99
94
53, 51, 49, 47, 45, 43, 41, 39,
37, 35, 33, 31, 29, 27, 25, 23
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
1, 75
2, 74
20, 56
21, 55
54, 50, 46, 42, 38, 34, 30, 26, 22
52, 48, 44, 40, 36, 32, 28, 24
84
83
82
81
80
79
78
77
76
85–93
V
CC
ESD
INPUT
ESD
ESD
AV
EE
Pin Description
Analog Inputs; xx = Channel Numbers 00 through 15.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling Edge Triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when High.
Disable Outputs, Active Low.
Chip Enable, Enable Low.
Must be low to clock in and latch data.
Selects Serial Data Mode, Low or Parallel Data Mode, High.
Must be connected.
Analog Outputs yy = Channel Numbers 00 Through 15.
Analog Ground for Inputs and Switch Matrix.
Must be connected.
5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
5 V for Inputs and Switch Matrix.
5 V for Output Amplifier that is shared by Channel Numbers xx and yy.
Must be connected.
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy.
Must be connected.
Parallel Data Input, TTL Compatible (Output Select LSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Input Select LSB).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select MSB).
Parallel Data Input, TTL Compatible (Output Enable).
No Connect.
V
CC
ESD
OUTPUT
RESET
ESD
V
CC
ESD
20k
AV
EE
DGND
a. Analog Input
b. Analog Output
c. Reset Input
V
CC
ESD
INPUT
ESD
V
CC
2k
ESD
OUTPUT
ESD
DGND
DGND
d. Logic Input
e. Logic Output
Figure 5. I/O Schematics
REV. A
–7–
AD [ ANALOG DEVICES ]
