AD8113
TIMING CHARACTERISTICS (Parallel)
Parameter
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to
UPDATE
Delay
UPDATE
Pulsewidth
Propagation Delay,
UPDATE
to Switch On or Off
CLK,
UPDATE
Rise and Fall Times
RESET
Time
Specifications subject to change without notice.
t
2
1
CLK
0
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
Limit
Min
20
100
20
100
0
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
100
200
t
4
t
1
D0–D4
A0–A2
1
0
t
3
t
5
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
6
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
V
IH
RESET, SER/PAR
CLK, D0, D1, D2, D3,
D4, A0, A1, A2, A3
CE, UPDATE
2.0 V min
V
IL
V
OH
V
OL
I
IH
RESET, SER/PAR
CLK, D0, D1, D2, D3,
D4, A0, A1, A2, A3
CE, UPDATE
20
µA
max
I
IL
RESET, SER/PAR
CLK, D0, D1, D2, D3,
D4, A0, A1, A2, A3
CE, UPDATE
–400
µA
min
I
OH
I
OL
RESET, SER/PAR
CLK, D0, D1, D2, D3,
D4, A0, A1, A2, A3
CE, UPDATE
DATA OUT DATA OUT
0.8 V max
2.7 V min
0.5 V max
DATA OUT DATA OUT
–400
µA
max 3.0 mA min
–4–
REV. A
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