AD8113
Table III. Operation Truth Table
SER/
CE
UPDATE CLK
DATA IN
DATA OUT
RESET
PAR Operation/Comment
1
0
X
1
X
f
X
Data i
X
X
1
X
0
No change in logic.
Data i-80
The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 80
clocks later.
0
1
f
D0 . . . D4,
A0 . . . A3
NA in Parallel
Mode
1
1
0
1
The data on the parallel data lines, D0–D4, are
loaded into the 80-bit serial shift register loca-
tion addressed by A0–A3.
Data in the 80-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
0
0
X
X
X
X
X
X
X
X
X
X
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D0
D1
D2
D3
D4
PARALLEL
DATA
(OUTPUT
ENABLE)
SER/PAR
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
DATA
OUT
D Q
CLK
D
Q
Q
D
D Q
CLK
D
Q
D
Q
D
Q
D
Q
D Q
CLK
D
Q
D
Q
D
Q
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
DATA IN
(SERIAL)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CE
UPDATE
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A0
A1
A2
A3
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE D
OUT0
B0
OUT0
B1
OUT0
B2
OUT0
B3
OUT0
EN
OUT1
B0
OUT14
EN
OUT15
B0
OUT15
B1
OUT15
B2
OUT15
B3
OUT15
EN
Q
Q
Q
Q
CLR
Q
Q
CLR
Q
Q
Q
Q
Q
CLR Q
RESET
(OUTPUT ENABLE)
DECODE
16
OUTPUT ENABLE
256
SWITCH MATRIX
Figure 4. Logic Diagram
–6–
REV. A
ADI [ ADI ]
