AD8113
300
250
200
150
INPUT
V
R
= ؎12V
= 600⍀
S
OUTPUT
2
– INPUT
L
V
R
= ؎5V
= 150⍀
S
100
50
0
L
OUTPUT
0
5
10
15
20
25
5ns/DIV
30
35
40
45
50
0
5
10
15
20
25
30
35
SERIES RESISTANCE – ⍀
TPC 13. Cap Load vs. Series Resistance for Less than 30%
Overshoot
TPC 16. Settling Time to 0.1%, 2 V Step, VS = 5 V,
RL = 150 Ω
10k
1k
100
10
1
10k
1k
100
10
1
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 14. Disabled Output Impedance vs. Frequency,
VS = 5 V
TPC 17. Disabled Output Impedance vs. Frequency,
VS = 12 V
1k
100
10
1k
100
10
1
1
0.1
0.1
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 15. Enabled Output Impedance vs. Frequency,
VS = 5 V
TPC 18. Enabled Output Impedance vs. Frequency,
VS = 12 V
REV. A
–11–
ADI [ ADI ]
