AD7846
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
DIP
Pin
Mnemonic
Description
1–3
4
DB2–DB0
VDD
Data I/O pins. DB0 is LSB.
Positive supply for analog circuitry. This is
+15 V nominal.
DB2
DB1
DB0
DB3
DB4
DB5
1
2
28
27
26
25
24
23
22
21
5
6
VOUT
RIN
DAC output voltage pin.
3
Input to summing resistor of DAC output
amplifier. This is used to select output
voltage ranges. See Table I.
V
4
LDAC
CLR
CS
DD
V
5
OUT
R
6
IN
AD7846
TOP VIEW
(Not to Scale)
7
8
VREF+
VREF–
VREF+ Input. The DAC is specified for VREF+
= +5 V.
V
V
7
R/W
REF+
8
V
REF–
CC
9
V
20 DGND
VREF– Input. For unipolar operation con-
nect VREF– to 0 V and for bipolar operation
connect it to –5 V. The device is specified
for both conditions.
SS
10
11
12
13
14
19
DB15
DB14
DB13
DB12
DB11
DB6
18
DB7
17
DB8
16
DB9
9
VSS
Negative supply for the analog circuitry.
This is –15 V nominal.
15
DB10
10–19 DB15–DB6
Data I/O pins. DB15 is MSB.
Ground pin for digital circuitry.
20
21
DGND
VCC
Positive supply for digital circuitry. This is
+5 V nominal.
PLCC
22
R/W
R/W input. This can be used to load data to
the DAC or to read back the DAC latch
contents.
4
3
2
1
28 27 26
23
24
CS
Chip select input. This selects the device.
CLR
Clear input. The DAC can be cleared to
000 . . . 000 or 100 . . . 000. See Table II.
PIN 1
IDENTIFIER
V
5
6
7
8
9
25
24
23
22
21
LDAC
CLR
CS
OUT
R
IN
V
V
REF+
25
LDAC
Asynchronous load input to DAC.
Data I/O pins.
AD7846
TOP VIEW
(Not to Scale)
R/W
REF–
26–28 DB5–DB3
V
V
SS
CC
DB15 10
DB14 11
20 DGND
19 DB6
Table I. Output Voltage Ranges
12 13 14 15 16 17 18
Output Range
VREF+
VREF–
RIN
0 V to +5 V
+5 V
+5 V
+5 V
+5 V
+5 V
0 V
0 V
–5 V
0 V
–5 V
VOUT
0 V
VOUT
+5 V
0 V
0 V to +10 V
+5 V to –5 V
+5 V to –5 V
+10 V to –10 V
REV. E
–5–
ADI [ ADI ]
