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AD7846JP 参数 Datasheet PDF下载

AD7846JP图片预览
型号: AD7846JP
PDF下载: 下载PDF文件 查看货源
内容描述: LC2MOS 16位电压输出DAC [LC2MOS 16-Bit Voltage Output DAC]
分类和应用:
文件页数/大小: 16 页 / 615 K
品牌: ADI [ ADI ]
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AD7846  
V
REF+  
SEGMENT 16  
R
R
DAC1  
DAC2  
R
V
IN  
S1  
S3  
S2  
S4  
DAC3  
A1  
A2  
A3  
OUT  
12 BIT DAC  
S15  
S17  
S14  
S16  
DB11DB0  
DB15DB12  
DB15DB12  
SEGMENT 1  
V
REF–  
Figure 16. D/A Conversion  
+15V  
+5V  
Output Stage  
The output stage of the AD7846 is shown in Figure 17. It is  
capable of driving a 2 k/1000 pF load. It also has a resistor  
feedback network which allows the user to configure it for gains  
of one or two. Table I shows the different output ranges that are  
possible.  
4
V
V
DD  
CC  
V
V
OUT  
(0V TO +10V)  
V
REF+  
OUT  
AD586  
R1  
An additional feature is that the output buffer is configured as a  
track-and-hold amplifier. Although normally tracking its input,  
this amplifier is placed in a hold mode for approximately 2.5 µs  
after the leading edge of LDAC. This short state keeps the DAC  
output at its previous voltage while the AD7846 is internally  
changing to its new value. So, any glitches that occur in the  
transition are not seen at the output. In systems where the  
LDAC is tied permanently low, the deglitching will not be in  
operation. Figures 8 and 9 show the outputs of the AD7846  
without and with the deglitcher.  
10k  
AD7846*  
C1  
1F  
R
IN  
V
REF–  
DGND  
V
SS  
SIGNAL  
GROUND  
*ADDITIONAL PINS  
OMITTED FOR CLARITY  
15V  
Figure 18. Unipolar Binary Operation  
Table III. Code Table for Figure 18  
R
IN  
10k  
10k⍀  
Binary Number  
in DAC Latch  
Analog Output  
(VOUT  
)
C1  
MSB  
LSB  
1111 1111 1111 1111  
1000 0000 0000 0000  
0000 0000 0000 0001  
0000 0000 0000 0000  
+10 (65535/65536) V  
+10 (32768/65536) V  
+10 (1/65536) V  
0
V
OUT  
DAC3  
ONE  
SHOT  
NOTE  
1 LSB = 10 V/216 = 10 V/65536 = 152 µV.  
LDAC  
Offset and gain may be adjusted in Figure 18 as follows: To  
adjust offset, disconnect the VREF– input from 0 V, load the  
DAC with all 0s and adjust the VREF– voltage until VOUT = 0 V.  
For gain adjustment, the AD7846 should be loaded with all 1s  
and R1 adjusted until VOUT = 10 (65535)/(65536) = 9.999847 V.  
If a simple resistor divider is used to vary the VREF– voltage, it is  
important that the temperature coefficients of these resistors  
match that of the DAC input resistance (–300 ppm/°C). Other-  
wise, extra offset errors will be introduced over temperature.  
Many circuits will not require these offset and gain adjustments.  
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be  
left open circuit and Pin 8 (VREF– ) of the AD7846 tied to 0 V.  
Figure 17. Output Stage  
UNIPOLAR BINARY OPERATION  
Figure 18 shows the AD7846 in the unipolar binary circuit  
configuration. The DAC is driven by the AD586, +5 V refer-  
ence. Since RIN is tied to 0 V, the output amplifier has a gain of  
2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is  
required, RIN should be tied to VOUT, configuring the output  
stage for a gain of 1. Table III gives the code table for the circuit  
of Figure 18.  
–8–  
REV. E