AD7846
These characteristics are included for design guidance and are not
subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V
to –15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V.)
AC PERFORMANCE CHARACTERISTICS
Limit at
TMIN to TMAX
(All Versions)
Parameter
Unit
Test Conditions/Comments
Output Settling Time1
6
9
7
µs max
µs max
V/µs typ
To 0.006% FSR. VOUT loaded. VREF– = 0 V. Typically 3.5 µs.
To 0.003% FSR. VOUT loaded. VREF– = –5 V. Typically 6.5 µs.
Slew Rate
Digital-to-Analog Glitch
Impulse
70
0.5
10
50
nV-secs typ
mV pk-pk typ
nV-secs typ
nV/√Hz typ
DAC alternately loaded with 10 . . . 0000 and
01 . . . 1111. VOUT unloaded.
VREF– = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s.
AC Feedthrough
Digital Feedthrough
Output Noise Voltage
Density 1 kHz–100 kHz
DAC alternately loaded with all 1s and all 0s. CS High.
Measured at VOUT. DAC loaded with 0111011 . . . 11.
VREF+ = VREF– = 0 V.
NOTES
1LDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ).
Specifications subject to change without notice.
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)
TIMING CHARACTERISTICS
Parameter
Limit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
0
60
0
60
0
120
10
60
0
70
0
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
R/W to CS Setup Time
CS Pulsewidth (Write Cycle)
R/W to CS Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Bus Relinquish Time
t8
t9
t10
t11
t12
CLR Setup Time
CLR Pulsewidth
CLR Hold Time
LDAC Pulsewidth
CS Pulsewidth (Read Cycle)
70
130
NOTES
1Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.
2t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
5V
3k⍀
DBN
DBN
100pF
DGND
100pF
3k⍀
DGND
t1
t3
t1
t3
5V
0V
R/ W
a. High Z to VOH
b. High Z to VOL
t12
t2
t4
5V
0V
CS
Figure 1. Load Circuits for Access Time (t6)
t5
t6
t7
5V
5V
0V
5V
DATA
DATA VALID
DATA VALID
3k⍀
t8
t9
t8
tt
99
t10
t10
DBN
DBN
10pF
10pF
3k⍀
DGND
CLR
0V
DGND
t11
5V
0V
LDAC
a. VOH to High Z
Figure 2. Load Circuits for Bus Relinquish Time (t7)
b. VOL to High Z
Figure 3. Timing Diagram
REV. E
–3–
ADI [ ADI ]
